PDF AKD5385B Data sheet ( Hoja de datos )

Número de pieza	AKD5385B
Descripción	24Bit 192kHz ADC
Fabricantes	Asahi Kasei Microsystems
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No Preview Available ! ASAHI KASEI [AK5385B] AK5385B 24Bit 192kHz ∆Σ ADC GENERAL DESCRIPTION The AK5385B is a 24bit, 192kHz sampling 2ch A/D converter for high-end audio system. The modulator in the AK5385B uses the Enhanced Dual Bit architecture and the AK5385B realizes high accuracy and low cost. The AK5385B performs 114dB dynamic range, so the device is suitable for AV-amp, AV recorder and musical instruments. The AK5385B is available in 28pin VSOP and SOP package, utilizing less board space. FEATURES Sampling Rate: 8kHz ~ 216kHz Full Differential Inputs S/(N+D): 103dB DR: 114dB S/N: 114dB High Performance Linear Phase Digital Anti-Alias filter • Passband: 0~21.768kHz (@fs=48kHz) • Ripple: 0.005dB • Stopband: 100dB Digital HPF Power Supply: 5V ± 5%(Analog), 3.0 ~ 5.25V(Digital) Power Dissipation: 183mW (@fs=48kHz) Package: 28pin SOP / 28pin VSOP AK5383/AK5393/AK5394A Semi-Pin compatible VCOM OVF M/S DFS1 DFS0 CKS1 CKS0 PDN VREFL LIN+ LIN- Delta-Sigma Modulator RIN+ RIN- VREFR Delta-Sigma Modulator Decimation Filter HPF Decimation Filter HPF Audio I/F Controller LRCK BICK MCLK SDTO TEST AVDD AVSS DVDD DVSS BVSS DIF HPFE Block diagram MS0406-E-00 -1- 2005/08 1 page ASAHI KASEI [AK5385B] Compare PCB layout example between AK5385B and AK5394A Analog Ground 0.1µ 0.1µ 10µ 1 VREFL+ VREFR+ 28 10µ 10µ 2 VREFL- VREFR- 27 10µ 0.22µ 3 VCOML 4 AINL+ 5 AINL- 3.0 ~ 5.25V Digital 6 ZCAL 0.1µ 7 VD 8 DGND 10µ 9 CAL VCOMR 26 AINR+ 25 0.22µ 5V AINR- 24 0.1µ Analog VA 23 AGND 22 BGND 21 10µ DFS1 20 10 RSTN HPFE 19 11 SMODE2 DFS0 18 12 SMODE1 MCLK 17 13 LRCK FSYNC 16 14 SCLK SDATA 15 AK5394A Analog Ground 0.1µ 0.1µ 10µ 1 VREFL VREFR 28 10µ (short) 2 AVSS AVSS 27 (short) 0.22µ 3 VCOM 4 LIN+ 5 LIN- 3.0 ~ 5.25V Digital 6 CKS0 0.1µ 7 DVDD 8 DVSS 10µ 9 OVF TEST 26 RIN+ 25 RIN- 24 0.1µ AVDD 23 5V Analog AVSS 22 BVSS 21 10µ DFS1 20 10 PDN HPFE 19 11 DIF DFS0 18 12 M/S MCLK 17 13 LRCK CKS1 16 14 BICK SDTO 15 AK5385B Pin # 1 2 6 9 11 12 16 27 26 28 AK5394A VREFL+ Lch Positive Voltage Reference Output Pin, 3.75V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL− with a 0.22µF ceramic capacitor. VREFL− Lch Negative Voltage Reference Output Pin, 1.25V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL+ with a 0.22µF ceramic capacitor. ZCAL Zero Calibration Control Pin This pin controls the calibration reference signal. CAL Calibration Active Signal Pin SMODE2 Serial Interface Mode Select Pin SMODE1 Serial Interface Mode Select Pin FSYNC Frame Synchronization Signal Pin VREFR− Rch Negative Voltage Reference Output Pin, 1.25V Normally connected to AGND with a large electrolytic capacitor and connected to VREFR+ with a 0.22µF ceramic capacitor. VCOMR Rch Common Voltage Pin, 2.75V VREFR+ Rch Positive Reference Output Voltage, 3.75V Normally connected to AGND with a large electrolytic capacitor and connected to VREFR− with a 0.22µF ceramic capacitor. AK5385B VREFL Lch Voltage Reference Input Pin, AVDD Normally, connected to AVSS with a 10µF electrolytic capacitor and a 0.1µF ceramic capacitor. AVSS Analog Ground Pin CKS0 Master Clock Select 0 Pin (Internal Pull-down Pin, typ. 100kΩ) OVF Analog Input Overflow Detect Pin DIF Audio Interface Format Pin M/S Master / Slave Mode Pin CKS1 Master Clock Select 1 Pin (Internal Pull-down Pin, typ. 100kΩ) AVSS Analog Ground Pin TEST Test Pin (Internal Pull-down Pin, typ. 100kΩ) VREFR Rch Voltage Reference Input Pin, AVDD Normally, connected to AVSS with a 10µF electrolytic capacitor and a 0.1µF ceramic capacitor. MS0406-E-00 -5- 2005/08 5 Page ASAHI KASEI [AK5385B] SWITCHING CHARACTERISTICS (Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 5.25V; CL=20pF) Parameter Symbol min Master Clock Timing Frequency fCLK 2.048 Pulse Width Low tCLKL 14.5 Pulse Width High tCLKH 14.5 LRCK Frequency Normal Speed Mode fsn 8 Double Speed Mode fsd 54 Quad Speed Mode fsq 108 Duty Cycle Slave mode 45 Master mode Audio Interface Timing Slave mode BICK Period Normal Speed Mode tBCK 1/128fsn Double Speed Mode tBCK 1/64fsd Quad Speed Mode tBCK 1/64fsq BICK Pulse Width Low tBCKL 33 Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO tBCKH tLRB tBLR tLRS tBSD 33 20 20 Master mode BICK Frequency fBCK BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO dBCK tMBLR tBSD −20 −20 Reset Timing PDN Pulse Width PDN “↑” to SDTO valid (Note 12) (Note 13) tPD tPDV 150 typ 50 64fs 50 516 max 27.648 54 108 216 55 Units MHz ns ns kHz kHz kHz % % ns ns ns ns ns ns ns 20 ns 20 ns Hz % 20 ns 20 ns ns 1/fs Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. The AK5385B can be reset by bringing the PDN pin = “L”. Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”. This value is in master mode This value is longer 1/fs in slave mode than master mode. MS0406-E-00 - 11 - 2005/08 11 Page

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