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PDF MC14043B Data sheet ( Hoja de datos )
| Número de pieza | MC14043B | |
| Descripción | CMOS MSI | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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1. MC14043B  Hay una vista previa y un enlace de descarga de MC14043B (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
CMOS MSI
Quad R–S Latches
The MC14043B and MC14044B quad R–S latches are constructed with
MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each latch has an independent Q output and set and
reset inputs. The Q outputs are gated through three–state buffers having a
common enable input. The outputs are enabled with a logical “1” or high on
the enable input; a logical “0” or low disconnects the latch from the Q
outputs, resulting in an open circuit at the Q outputs.
• Double Diode Input Protection
• Three–State Outputs with Common Enable
• Outputs Capable of Driving Two Low–power TTL Loads or One Low–
Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
MC14043B
MC14044B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
MC14043B
4
S0
2
Q0
MC14044B
4
R0
13
Q0
3
R0
6
S1
9
Q1
3
S0
6
R1
9
Q1
7
R1
12
S2
10
Q2
VDD = PIN 16
VSS = PIN 8
NC = PIN 13
7
S1
12
R2
10
Q2
VDD = PIN 16
VSS = PIN 8
NC = PIN 2
11
R2
14
S3
15
R3
5
ENABLE
REV 3
1/94
©MMCot1or4o0la4, I3nBc. 1M99C514044B
162
1 TRUTH TABLE
Q3 S R E
Q
X X 0 High
Impedance
0 0 1 No Change
011
0
101
1
111
1
X = Don’t Care
11
S2
14
R3
15
S3
5
ENABLE
1
Q3
TRUTH TABLE
SRE
Q
X X 0 High
Impedance
001
0
011
1
101
0
1 1 1 No Change
X = Don’t Care
MOTOROLA CMOS LOGIC DATA
1 page  
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16 9
–B–
18
CL
–T–
SEATING
PLANE
F
NK
E
G
D 16 PL
0.25 (0.010) M T A S
M
J 16 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC
1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC
7.62 BSC
M 0_ 15_ 0_ 15_
N 0.020 0.040 0.51 1.01
–A–
16
1
H
G
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
9
B
8
FC
S
L
–T–
SEATING
PLANE
KJ
D 16 PL
0.25 (0.010) M T A M
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC
2.54 BSC
H 0.050 BSC
1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0_ 10_ 0_ 10 _
S 0.020 0.040 0.51 1.01
MC14043B MC14044B
166
MOTOROLA CMOS LOGIC DATA
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MC14043B.PDF ] | |
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