|
|
PDF CDP68HC68A2 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC68A2 | |
| Descripción | CMOS Serial 10-Bit A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CDP68HC68A2 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
CDP68HC68A2
July 1998
CMOS Serial 10-Bit A/D Converter
Features
• 10-Bit Resolution
• 8-Bit Mode for Single Data Byte Transfers
• SPI (Serial Peripheral Interface) Compatible
• Operates Ratiometrically Referencing VDD or an
External Source
• 14µs 10-Bit Conversion Time
• 8 Multiplexed Analog Input Channels
• Independent Channel Select
• Three Modes of Operation
• On Chip Oscillator
• Low Power CMOS Circuitry
• Intrinsic Sample and Hold
• 16 Lead Dual-In-Line Plastic Package
• 20 Lead Dual-In-Line Small Outline Plastic Package
• Evaluation Board available - CDP68HC05C16BEVAL
Ordering Information
TEMP. RANGE
PART NUMBER (oC) PACKAGE
PKG.
NO.
CDP68HC68A2E
-40 to 85 16 Ld PDIP E16.3
CDP68HC68A2M
-40 to 85 20 Ld SOIC M20.3
Description
The CDP68HC68A2 is a CMOS 8-bit or 10-bit successive
approximation analog to digital converter (A/D) with a
standard Serial Peripheral Interface (SPI) bus and eight mul-
tiplexed analog inputs. Voltage referencing is user selectable
to be relative to either VDD or analog channel 0 (AI0). The
analog inputs can range between VSS and VDD.
The CDP68HC68A2 employs a switched capacitor,
successive approximation A/D conversion technique which
provides an inherent sample-and-hold function. An onchip
Schmitt oscillator provides the internal timing for the A/D
converter. The Schmitt input can be externally clocked or
connected to a single, external capacitor to form an RC
oscillator with a period of approximately 10-30ns per
picofarad.
Conversion times are proportional to the oscillator period. At
the maximum specified frequency of 1MHz, 10-bit
conversions take 14µs per channel. At the same frequency,
8-bit conversions consume 12µs per channel.
The versatile modes of the CDP68HC68A2 allow any
combination of the eight input channels to be enabled and
any one of the selected channels to be specified as the
“starting” channel. Conversions proceed sequentially
beginning with the starting channel. Nonselected channels
are skipped. Modes can be selected to: sequence from
channel to channel on command; sequence through
channels automatically, converting each channel one time;
or sequence repeatedly through all channels.
The results of 10-bit conversions are stored in 8-bit register
pairs (one pair per channel). The two most significant bits
are stored in the first register of each pair and the eight least
significant bits are stored in the second register of the pair.
To allow faster access, in the 8-bit mode, the results of
conversions are stored in a single register per channel.
A read-only STATUS register facilitates monitoring the
status of conversions. The STATUS register can simply be
polled or the INT pin can be enabled for interrupt driven
communications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 1963.3
1 page  
CDP68HC68A2
Through this specification the CDP68HC68A2 is referred to
simply as the A2.
Functional Pin Description
OSC - Oscillator (Input/Output)
This pin is user programmable. In the “external” mode, the
clock input for the successive approximation logic is applied
to OSC from an external clock source. The input is a Schmitt
trigger input which provides excellent noise immunity. In the
“internal” mode, a capacitor is connected between this pin
and a power supply to form a “one pin oscillator”. The
frequency of the oscillator is inversely dependent on the
capacitor value. Differences in period, from one device to
another, should be anticipated. Systems utilizing the internal
oscillator must be tolerant of uncertainties in conversion
times or provide trimming capability on the OSC capacitor.
See Table 2 for typical frequencies versus capacitance.
INT - Interrupt (Open Drain Output)
INT is used to signal the completion of an A/D conversion.
This output is generally connected, in parallel with a pullup
resistor, to the interrupt input of the controlling microproces-
sor. The open drain feature allows wire-NOR’ing with other
interrupt inputs. The inactive state of INT is high impedance.
When active, INT is driven to a low level output voltage. The
state of INT is controlled and monitored by bits in the Mode
Select and Status Registers.
MISO - Master-In-Slave-Out (Output)
Serial data is shifted out on this pin. Data is provided most
significant bit first.
MOSI - Master-Out-Slave-In (Input)
Serial data is shifted in on this pin. Data must be supplied
most significant bit first. This is a CMOS input and must be
held high or low at all times to minimize device current.
SCK - Serial Clock (Input)
Serial data is shifted out on MISO, synchronously, with each
leading edge of SCK. Input data from the MOSI pin is
latched, synchronously, with each trailing edge of SCK.
CE - Chip Enable (Input)
An active HIGH device enable. CE is used to synchronize
communications on the SPI lines (MOSI, MISO, and SCK).
When CE is held in a low state, the SPI logic is placed in a
reset mode with MISO held in a high impedance state.
Following a transition from low to high on CE, the
CDP68HC68A2 interprets the first byte transferred on the
SPI lines as an address. If CE is maintained high,
subsequent transfers are interpreted as data reads or writes.
AIO/EXT REF - Analog Input 0/External Reference (Input)
This input is one of eight analog input channels. Its function
is selectable through the Mode Select Register (MSR). If VR
is set high in the MSR, AI0/EXT REF provides an external
voltage reference against which all other inputs are
measured. AI0/EXT REF must fall within the VSS and VDD
supply rails. If VR is set low in the MSR, VDD is used as the
reference voltage and AI0/EXT REF is treated as any other
analog input (see AI1-AI7).
AI1-AI7 - Analog Inputs 1-7 (Inputs)
Together with AI0/EXT REF, these pins provide the eight
analog inputs (channels) which are multiplexed within the
CDP68HC68A2 to a single, high-speed, successive approxi-
mation, A/D converter. AI1-AI7 must fall within the VSS and
VDD supply rails.
VSS - Negative Power Supply
This pin provides the negative analog reference and the
negative power supply for the CDP68HC68A2.
VDD - Positive Power Supply
This pin provides the positive power supply and, depending
on the value of the VR bit in the MSR, the positive analog
reference for the CDP68HC68A2.
Overview
From the programmer’s perspective, the A2 is comprised of
three control registers (Mode Select Register - MSR,
Channel Select Register - CSR, and Starting Address
Register - SAR), a status register (SR), an array of eight
pairs of Data Registers, and one non-addressable, internal
register (Channel Address Register). See Figure 1.
The A2 contains a high speed, 10-bit, successive
approximation, analog to digital converter (A/D). The input to
the A/D can be any one of the A2’s eight analog inputs (AI0
through AI7). The contents of the CAR determine which ana-
log input is connected to the A/D. The result of each analog
to digital conversion is written to the Data Register array. The
Data Register array is also addressed by the contents of the
CAR, providing a one to one correspondence between each
analog input and each Data Register pair.
The contents of the CAR are also used during Data Register
reads to address the Data Register array. The CAR is
automatically jammed with the correct address when an
Address/Control Byte is sent to the A2. A second means, to
initialize the CAR, is by writing to the SAR.
Normal procedure for programming the A2 is to first select
the desired hardware mode by writing to the MSR. The
“active” analog channels are then specified by writing to the
CSR (channels not selected in the CSR are skipped during
conversions and burst mode reads). Finally, a write to the
SAR initializes the CAR (designating the first channel to
convert) and initiates the A/D conversions.
Polling of the SR or hardware interrupts can be used to
determine the completion of conversions.
The converted data is read from the data registers. In eight
bit mode, a single register is read for each channel of inter-
est. In ten bit mode, two registers are read per channel.
5
5 Page 
CDP68HC68A2
When all channels have been converted the INT and ACC
flags in the SR are set, the INT pin is driven low (if IE is true
in the MSR), the CIP flag is cleared, and, if active, the
internal oscillator is disabled.
Data Registers can safely be read after all channels have
been converted. If the starting channel was a channel active
in the CSR then the CAR will one again be pointing to that
channel (providing all channels had been read or CSR or
MSR written since the last set of conversions - see Note
below). IF a read from a Data Register, other than the one
first converted, is performed, the CAR must be set to the
desired register prior to sending the Address/Control Byte.
Setting CAR is done by writing the SAR with ENC = 0, SAE
= 1, and the CA2 - CA0 bits equal to the desired channel.
NOTE: A write to the SAR does not clear the DV flag for each chan-
nel. This implies that if: conversions are completed on all registers
selected in CSR; conversions stopped; an incomplete read of the
Data Registers is performed; and conversions reinitiated with a write
to the SAR - some DVs will still be set. In Mode 2, which terminates
when all DVs are true (ACC goes true), unread channels may not be
converted unless CSR is written to before setting ENC.
There are two ways to prematurely stop conversions in Mode
2. The first is to perform any “abort” action (see Abort Modes).
Performing an abort, may produce spurious conversion val-
ues. The second, and preferred means to stop a Mode 2 con-
version, is to clear the ENC bit by writing a $00 to the SAR.
Clearing ENC will synchronously stop conversions at the end
of the current conversion. When prematurely stopping conver-
sions, CIP is not valid. The CIP flag cannot be used to deter-
mine when the current conversion is complete. Instead, a time
delay equal to one conversion time must be built into the soft-
ware. The appropriate delay will ensure the last conversion is
complete before Data Register reads begin.
conversions in Mode 3. The first is to perform any “abort”
action (see Abort Modes). Performing an abort, may pro-
duce spurious conversion values. The second, and preferred
means to stop a Mode 3 conversion, is to clear the ENC bit
by writing a $00 to the SAR. Clearing ENC will
synchronously stop conversions at the end of the current
conversion. CIP is not valid following the clearing of ENC.
The CIP flag cannot be used to determine when the current
conversion is complete. Instead, a time delay equal to one
conversion time must be built into the software. The
appropriate delay will ensure the last conversion is complete
before Data Register reads begin.
The Data Registers can safely be read after ENC is cleared
and one conversion time has elapsed. One remaining task is
to be certain the contents of the CAR match the address
sent in the Address/Control Byte. This is done by jamming
the CAR with a write to the SAR with ENC = 0, SAE = 1, and
CA2 - CA0 equal to the desired channel address.
Abort Modes
Any active mode can be aborted by any one of the following
means:
1. A write to the MSR
2. A write to the CSR
3. A write to the SAR with ENC and/or SAE = 1
4. A read of any Data Register
The contents of Data Registers are not guaranteed following
an abort. Writing a $00 to the MSR is equivalent to a reset.
To synchronously stop conversions in Modes 2 or 3 set the
SAR to $00 (See Mode 2 and Mode 3).
Prematurely stopping the conversions leaves the CAR in an
unknown state. One remaining task, before Data Registers
are read, is to be certain the contents of the CAR match the
address sent in the Address/Control Byte. This is done by
jamming the CAR with a write to the SAR with ENC = 0,
SAE = 1, CA3 - C A2 - CA0 equal to the desired channel
address.
Mode 3 - Continuous Scan
Analog Inputs
Shown in Figure 5 is a simplified equivalent circuit represent-
ing the input to the Analog to Digital Converter through the
multiplexer as seen from each AIn pin.
Due to the nature of the switched capacitor array used by the
successive approximation A/D, two important points are
noted here:
In Mode 3, when ENC is set in the SAR, conversions are
performed on all channels selected in the CSR. COnversion
begin on the channel specified by the CAR (this channel
does not have to be active in the CSR) and proceed in
ascending order for all channels selected in the CSR. Each
time the highest active channel is done converting, the CAR
advances to the lowest active channel and continues from
that point.
When ENC is set in the SAR, the internal clock is activated
(if selected) and conversions begin.
When all channels have been converted one time the ACC
flag in the SR is set. This is the only valid status flag in Mode
3. The CIP flag is not valid in Mode 3. The INT flag and the
INT pin are both held in a disabled state during Mode 3.
Data Registers cannot be read until Mode 3 conversions
have been terminated. There are two ways to stop
1. A property of capacitive input is the intrinsic sample and
hold function. This provides all that is necessary to
accurately sample a point on an input waveform within
the input bandwidth shown in the specifications (under
1.5 conversion oscillator cycles).
2. The input to the capacitor network appears as an RC
network with a time constant and therefore places
constraints on the source impedance. The charging time
and therefore the accuracy of the conversion will be ad-
versely affected by increasing the source impedance.
It is recommended to set the conversion oscillator frequency
in accordance with the input impedance in order to allow
sufficient time (the 1.5 TOSC cycles) to sample a changing
waveform through the modeled input low pass filter network
which includes the input source in a series circuit with the
internal impedance.
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CDP68HC68A2.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CDP68HC68A2 | CMOS Serial 10-Bit A/D Converter |  GE |
| CDP68HC68A2 | CMOS Serial 10-Bit A/D Converter | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |