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PDF DS3100 Data sheet ( Hoja de datos )

Número de pieza DS3100
Descripción Stratum 2/3E/3 Timing Card IC
Fabricantes Microsemi　
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Data Sheet
April 2012
DS3100
Stratum 2/3E/3 Timing Card IC
General Description
When paired with an external TCXO or OCXO, the
DS3100 is a complete central timing and
synchronization solution for SONET/SDH network
elements. With two multiprotocol BITS/SSU receivers
and 14 input clocks, the device directly accepts both
external timing and line timing from a large number of
line cards. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the Stratum 2,
3E, 3, 4E and 4 requirements of GR1244, GR-253,
G.812 Types I – IV, G.813 and G.8262. From the output
of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3100 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3100 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs.
Applications
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
Functional Diagram
TIMING FROM
LINE CARDS
(VARIOUS RATES) 14
TIMING FROM
BITS/SSU
(DS1, E1, CC, ETC.) 2
LOCAL TCXO
OR OCXO
DS3100
SONET/SDH
Synchronization IC
2
11
TIMING TO BITS/SSU
(DS1, E1, CC, ETC.)
TIMING TO
LINE CARDS
(VARIOUS RATES)
CONTROL STATUS
Features
Synchronization Subsystem for Stratum 2, 3E,
3, 4E and 4 plus SMC, SEC and EEC
- Meets Requirements of GR-1244 Stratum 2 - 4,
GR-253, G.812 Types I - IV, G.813 and G.8262
- Stratum 2, 3E or 3 Holdover Accuracy with
Suitable External Oscillator
- Programmable Bandwidth, 0.5mHz to 70Hz
- Hitless Reference Switching on Loss of Input
- Phase Build-Out and Transient Absorption
- Locks to and Generates 125MHz for Gigabit
Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
- 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
- Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
- Two 64kHz Composite Clock Receivers
- Continuous Input Clock Quality Monitoring
- Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
- Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
- Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
- One 64kHz Composite Clock Transmitter
- One 1.544MHz/2.048MHz Output Clock
- Two Sync Pulses: 8kHz and 2kHz
- Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
Two Multiprotocol BITS/SSU Transceivers
- Receive and Transmit DS1, E1, 2048kHz, and
6312kHz Timing Signals
- Insert and Extract SSM Messages (DS1, E1)
- Automatically Invalidate Clocks on LOS, OOF,
AIS, and Other Defects
Internal Compensation for Master Clock
Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
Ordering Information
PART
DS3100GN
DS3100GN+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
256 CSBGA (17mm) 2
256 CSBGA (17mm) 2
+Denotes a lead(Pb)-free/RoHS-compliant package.
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DS3100 pdf
DS3100
LIST OF FIGURES
Figure 2-1. DS3100 Block Diagram ............................................................................................................................. 8
Figure 3-1. Typical Application Example ..................................................................................................................... 9
Figure 7-1. T0 DPLL State Transition Diagram ......................................................................................................... 34
Figure 7-2. T4 DPLL State Transition Diagram ......................................................................................................... 37
Figure 7-3. Typical MTIE for T0 DPLL Output ........................................................................................................... 43
Figure 7-4. Typical TDEV for T0 DPLL Output .......................................................................................................... 44
Figure 7-5. DPLL Block Diagram ............................................................................................................................... 46
Figure 7-6. OC10 8kHz Options ................................................................................................................................ 54
Figure 7-7. BITS Transceiver Block Diagram ............................................................................................................ 58
Figure 7-8. BITS Transceiver Master Clock PLL Block Diagram .............................................................................. 59
Figure 7-9. BITS Transmitter Clock Mux Block Diagram........................................................................................... 60
Figure 7-10. BITS Transceiver External Components............................................................................................... 62
Figure 7-11. Jitter Tolerance, DS1 Mode................................................................................................................... 63
Figure 7-12. Jitter Tolerance, E1 and 2048kHz Modes ............................................................................................. 64
Figure 7-13. Transmit Pulse Template, DS1 Mode ................................................................................................... 66
Figure 7-14. Transmit Pulse Template, E1 Mode...................................................................................................... 66
Figure 7-15. Transmit Pulse Template, 2048kHz Mode ............................................................................................ 67
Figure 7-16. FAS/Si/RAI/Sa Source Logic................................................................................................................. 72
Figure 7-17. GR-378 Composite Clock Pulse Mask.................................................................................................. 76
Figure 7-18. SPI Clock Polarity and Phase Options.................................................................................................. 78
Figure 7-19. SPI Bus Transactions............................................................................................................................ 79
Figure 9-1. JTAG Block Diagram............................................................................................................................. 198
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 200
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 204
Figure 10-2. Recommended Termination for LVPECL Pins.................................................................................... 205
Figure 10-3. Recommended External Components for AMI Composite Clock Pins ............................................... 206
Figure 10-4. BITS Receiver Timing Diagram........................................................................................................... 208
Figure 10-5. BITS Transmitter Timing Diagram....................................................................................................... 209
Figure 10-6. Parallel Interface Timing Diagram (Nonmultiplexed) .......................................................................... 211
Figure 10-7. Parallel Interface Timing Diagram (Multiplexed) ................................................................................. 212
Figure 10-8. SPI Interface Timing Diagram ............................................................................................................. 213
Figure 10-9. JTAG Timing Diagram......................................................................................................................... 214
Figure 11-1. DS3100 Pin Assignment—Left Half .................................................................................................... 219
Figure 11-2. DS3100 Pin Assignment—Right Half.................................................................................................. 220
LIST OF TABLES
Table 1-1. Applicable Telecom Standards................................................................................................................... 7
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 15
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 16
Table 6-3. BITS Receiver Pin Descriptions ............................................................................................................... 17
Table 6-4. BITS Transmitter Pin Descriptions ........................................................................................................... 18
Table 6-5. Global Pin Descriptions ............................................................................................................................ 19
Table 6-6. Parallel Interface Pin Descriptions ........................................................................................................... 20
Table 6-7. SPI Bus Mode Pin Descriptions ............................................................................................................... 21
Table 6-8. JTAG Interface Pin Descriptions .............................................................................................................. 21
Table 6-9. General-Purpose I/O Pin Descriptions ..................................................................................................... 21
Table 6-10. Power-Supply Pin Descriptions .............................................................................................................. 22
Table 7-1. GR-1244 Stratum 2/3E/3 Stability Requirements..................................................................................... 25
Table 7-2. Input Clock Capabilities ............................................................................................................................ 27
Table 7-3. Locking Frequency Modes ....................................................................................................................... 28
Table 7-4. Default Input Clock Priorities .................................................................................................................... 31
Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 38
Table 7-6. T0 Adaptation for T4 Phase Measurement Mode .................................................................................... 42
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DS3100 arduino
DS3100
of-the-art LIU receivers with software-selectable termination and high-impedance inputs to support redundant
timing cards without relays in the signal path.
The Output Clock Synthesizer and Selector (OCSS) block shown in Figure 2-1 contains the T0 output APLL, the T4
output APLL, clock divider logic, and additional output DFS blocks. The T0 and T4 APLLs multiply the clock rates
from the DPLLs by four and simulataneously attenuate jitter. Using the different settings of the T0 and T4 DPLLs
and the output divider logic, the DS3100 can produce more than 60 different output frequencies including common
SONET/SDH, PDH and synchronous Ethernet rates plus 2kHz and 8kHz frame pulses.
In addition to creating digital clock signals for use within the system, the DS3100 can also directly transmit one
composite clock signal on its OC8 pin and up to two DS1, E1, or 2048kHz synchronization signals using its BITS
transmitters. These signals typically convey the recovered timing from one SONET/SDH port to a nearby BITS
timing-signal generator or SSU which in turn distributes timing to the whole central office.The BITS transmitters are
full-featured frame formatters and LIU transmitters capable of generating DS1/E1 frames, inserting incoming SSM
messages, and driving both short-haul and long-haul signals. Any of the output clock signals can be connected to
either of the BITS transmitters for use as the transmission clock. The analog front-ends of the BITS transmitters are
state-of-the-art LIU transmitters with software-selectable termination and high-impedance outputs to support
redundant timing cards without relays in the signal path.
The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus the free-run and
holdover stability of the DS3100-based timing card is entirely a function of the stability of the external oscillator, the
performance of which can be selected to match the application: TCXO, OCXO, double-oven OCXO, etc. The
12.8MHz clock from the external oscillator is multiplied by 16 by the Master Clock Generator block to create the
204.8MHz master clock used by the rest of the device. Since every block on the device depends on the master
clock and therefore the local oscillator clock for proper operation, the master clock generator has a watchdog timer
(WDT) function that can be used to signal a local microprocessor in the event of a local oscillator clock failure.
The DS3100 also has several features to support master/slave timing card redundancy and protection. Two
DS3100 devices on redundant cards can be configured to maintain the same priority tables, choose the same input
references, and generate output clocks and frame syncs with the same frequency and phase.
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