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PDF PCF85063BTL Data sheet ( Hoja de datos )

Número de pieza PCF85063BTL
Descripción Tiny Real-Time Clock/calendar
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCF85063BTL Hoja de datos, Descripción, Manual

PCF85063BTL
Tiny Real-Time Clock/calendar with alarm function and
SPI-bus
Rev. 6 — 18 November 2015
Product data sheet
1. General description
The PCF85063BTL is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low
power consumption. An offset register allows fine-tuning of the clock. All addresses and
data are transferred serially via a Serial Peripheral Interface (SPI-bus) with a maximum
data rate of 7 Mbit/s. The register address is incremented automatically after each written
or read data byte.
For a selection of NXP Real-Time Clocks, see Table 46 on page 49.
2. Features and benefits
Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
Clock operating voltage: 0.9 V to 5.5 V
Low current; typical 0.22 A at VDD = 3.3 V and Tamb = 25 C
3 line SPI-bus with a maximum data rate of 7 Mbit/s
Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz,
8.192 kHz, 4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz)
Selectable integrated oscillator load capacitors for CL = 7 pF or CL = 12.5 pF
Alarm function
Countdown timer
Minute and half minute interrupt
Oscillator stop detection function
Internal Power-On Reset (POR)
Programmable offset register for frequency adjustment
3. Applications
Digital still camera
Digital video camera
Printers
Copy machines
Mobile equipment
Battery powered devices
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

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PCF85063BTL pdf
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8.1 Registers organization
Table 5. Registers overview
Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 8 on page 10.
Address Register name Bit
76543210
Control and status registers
00h Control_1
EXT_TEST -
STOP
SR
-
CIE
12_24
CAP_SEL
01h Control_2
AIE
AF
MI
HMI TF
COF[2:0]
02h Offset
MODE
OFFSET[6:0]
03h RAM_byte
B[7:0]
Time and date registers
04h Seconds
OS
SECONDS (0 to 59)
05h Minutes
-
MINUTES (0 to 59)
06h Hours
-
-
AMPM HOURS (1 to 12) in 12 hour mode
HOURS (0 to 23) in 24 hour mode
07h Days - - DAYS (1 to 31)
08h Weekdays
-
-
-
-
-
WEEKDAYS (0 to 6)
09h Months
-
-
-
MONTHS (1 to 12)
0Ah Years
YEARS (0 to 99)
Alarm registers
0Bh
Second_alarm AEN_S
SECOND_ALARM (0 to 59)
0Ch
Minute_alarm AEN_M
MINUTE_ALARM (0 to 59)
0Dh
Hour_alarm
AEN_H
-
AMPM HOUR_ALARM (1 to 12) in 12 hour mode
HOUR_ALARM (0 to 23) in 24 hour mode
0Eh
Day_alarm
AEN_D
-
DAY_ALARM (1 to 31)
0Fh
Weekday_alarm AEN_W
-
-
-
-
WEEKDAY_ALARM (0 to 6)
Timer registers
10h
Timer_value
T[7:0]
11h
Timer_mode
-
-
-
TCF[1:0]
TE TIE TI_TP
Reference
Section 8.2.1
Section 8.2.2
Section 8.2.3
Section 8.2.4
Section 8.3.1
Section 8.3.2
Section 8.3.3
Section 8.3.4
Section 8.3.5
Section 8.3.6
Section 8.3.7
Section 8.5.1
Section 8.5.2
Section 8.5.3
Section 8.5.4
Section 8.5.5
Section 8.6.1
Section 8.6.2

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PCF85063BTL arduino
NXP Semiconductors
PCF85063BTL
Tiny Real-Time Clock/calendar with alarm function and SPI-bus
The PCF85063BTL resets to:
Time — 00:00:00
Date — 20000101
Weekday — Saturday
8.2.2 Register Control_2
Table 9. Control_2 - control and status register 2 (address 01h) bit description
Bit Symbol
Value
Description
7 AIE
alarm interrupt
0[1] disabled
1 enabled
6 AF
alarm flag
0[1] read: alarm flag inactive
write: alarm flag is cleared
1 read: alarm flag active
write: alarm flag remains unchanged
5 MI
minute interrupt
0[1] disabled
1 enabled
4 HMI
half minute interrupt
0[1] disabled
1 enabled
3 TF
timer flag
0[1] no timer interrupt generated
1 flag set when timer interrupt generated
2 to 0 COF[2:0]
see Table 11 CLKOUT control
[1] Default value.
Reference
Section 8.2.2.1
Section 8.5.6
Section 8.2.2.1
Section 8.5.6
Section 8.2.2.2
Section 8.2.2.3
Section 8.2.2.2
Section 8.2.2.3
Section 8.2.2.1
Section 8.2.2.3
Section 8.6.3
Section 8.2.2.4
PCF85063BTL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 18 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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