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기능 Scalable VGA to NTSC/PAL Encoder
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CH7002D-V 데이터시트, 핀배열, 회로
CHRONTEL
CH7002D
Preliminary
Scalable VGA to NTSC/PAL Encoder
Features
• Fully integrated solution for PC to TV display
• TrueScale TM rendering engine supports underscan
operation for both 640x480 or 800x600 inputs
• Advanced 3-line digital flicker filtering with
programmable algorithm selections
• Fully programmable through I2C port or hardware
(pin-based) controls
• Wide range of VGA software drivers for full
synchronization and image positioning
• Auto-detection of TV presence
• Programmable power management features three
power-down modes
• Supports both NTSC and PAL (B, D, G, H, or I) TV
formats onto both composite and S-Video
• Triple 8-bit ADC inputs and triple 8-bit DAC outputs
• On-chip reference generation and loop filter
• Offered in 44-pin PLCC package
General Description
Chrontel’s CH7002 VGA to NTSC/PAL encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It accepts RGB analog inputs directly
from VGA controllers and converts them directly into NTSC
or PAL TV format, with simultaneous composite and
S-Video outputs.
This circuit integrates a digital NTSC/PAL encoder with 8-
bit ADC and DAC interfaces, a 3-line vertical filter, and low-
jitter phase-locked loop to create outstanding quality video.
Through Chrontel’s TrueScale TM rendering technology, the
CH7002 supports full vertical and horizontal underscan
operation from either 640x480 or 800x600 input to either
NTSC or PAL outputs.
A high level of performance along with full programmability
makes the CH7002 ideal for system-level PC or Web
browser solutions. All features are software programmable,
through a standard I2C port, to enable fully integrated system
solutions by using a TV as the primary display device.
Patent number 5,781,241
PMODE
SD SC ADDR
I2C REGISTER & CONTROL
BLOCK
LINE
MEMORY
RSET
RSET
RR
ADC
Y
LINE RENDERING ENGINE
G
G COLOR
U
ADC
SPACE
-SCALING
CONVERTER
-DEFLICKERING
BB
V -SCAN CONVERSION
ADC
SYSTEM CLOCK
Y
U DIGITAL
NTSC/PAL
ENCODER
V & FILTER
DAC
DAC
DAC
VREF
PLL
TIMING & SYNC GENERATOR
OSC
VREF1 VREF2
XCLK
HV
Figure 1: Functional Block Diagram
XI XO
Y
CVBS
C
CLKOUT
201-0000-029 Rev 6.1, 8/2/99
1




CH7002D-V pdf, 반도체, 판매, 대치품
CHRONTEL
CH7002D
Table 1. Pin Description (continued)
44-Pin
PLCC
22
9, 11, 12,
13
28
29
30
32
35
34
Type
Out
In
In
In/Out
In
In
In
In
Symbol
Description
C
UP,
DOWN,
LEFT,
RIGHT
RESET*/D
M0
SD/DM1
SC/DM2
XCLK/SD3
V
H
Chrominance Output
A 75 termination resistor, with short traces, should be attached between C
and ground for optimum performance. Use of additional filters is discussed in
the Application Information section.
Position Controls (low-to-high transition, internal pull-up)
UP, DOWN, LEFT, and RIGHT, allows the screen display position to be
moved incrementally, in each respective direction, for every toggle of this pin
to ground. An internal schmitt trigger minimizes switch bounce problems.
These pins may be connected directly to the power supply or ground.
Reset (active low) /Display Mode Select [0] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), the RESET*/DM0 pin becomes
RESET*. In this mode, when RESET* is held high (default), the chip is in
operating state, and when RESET* is pulled low, the entire chip is reset and
initialized to its power-up state.
When the PMODE pin is pulled low, this pin becomes DM0, which combined
with DM1 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described in Application Information and Registers
and Programming sections.
Serial Data/Display Mode Select [1] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SD, the serial
data pin of the I2C interface port.
When the PMODE pin is pulled low, this pin becomes DM1, which combined
with DM0 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described under the programming section.
Serial Clock/Display Mode Select [2] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SC, the serial
clock pin of the I2C interface port.
When the PMODE pin is pulled low, this pin becomes DM2, which combined
with DM0 and DM1, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described in the Registers and Programming and
Application Information sections.
External Clock/Sample Delay (bit 3) (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes XCLK or
external clock, which accepts an external pixel clock input.
When the PMODE pin is pulled low, this pin becomes SD3 or Sample Delay,
the function corresponding to bit 3 of the Sample Delay register, which
provides the following selection:
SD3 Sample Delay Selected
1 20 ns nominal delay
0 0 delay (default)
This pin-programming is “mux-ed” with the Sample Delay register (bit 3). All
related modes are described in the Registers and Programming section.
Vertical Sync Input
This pin accepts the vertical sync output from the VGA card. The capacitive
loading on this pin should be kept to a minimum.
Horizontal Sync Input
This pin accepts the horizontal sync output from the VGA card. The
capacitive loading on this pin should be kept to a minimum. Refer to the
Application Information section for PC Board layout considerations.
4 201-0000-029 Rev6.1, 8/2/99

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CH7002D-V 전자부품, 판매, 대치품
CHRONTEL
CH7002D
Clock Generation and Video Timing
All clock signals of the CH7002 are generated from the VGA synchronization inputs by a low-jitter, PLL circuit.
The VGA input and sync timing are illustrated in Figures 3, 5 and 6. The VGA pixel clock is generated internally,
using the VGA horizontal sync signal, and is used for sampling the RGB inputs pixel-by-pixel, which aids in
preventing aliasing artifacts. All synchronization and color burst envelope pulses are internally generated, using
only the timing signals provided by the VGA synchronization inputs.
In situations where the CH7002 is placed next to a graphics controller (e.g. motherboard or add-in cards), the
graphics pixel clock can be provided to CH7002, directly from the graphics controller via pin XCLK. This
arrangement minimizes phase jitter of the system clock used in the encoder. See the sections on Application
Information and Registers and Programming for detailed information on how to connect and enable this function.
31.78 µs
H
R,G,B
DATA
3.81 µs
25.42 µs
ACTIVE VIDEO
1.91 µs
0.64 µs
Note: The timing diagram shown is for 640 x 480, 60 Hz VGA mode
Figure 3: Typical VGA Input Timing
31.78 µs
H
V*
(ACTIVE LOW)
63.56 µs
Figure 4: VGA Horizontal and Vertical Sync Input Timing
Note: The values shown in Figures 4 and 5 represent typical timing parameters for VGA controllers operating in 640x480
resolution at 60 Hz, with the CH7002 in overscan mode. Other resolutions and display modes have different timing
requirements.
EXT
PCLK
HSYNC and
VSYNC
t1
EXT
PCLK
HSYNC anVd
VSSYYNNCC
t2
Figure 5: External Clock Input Timing
201-0000-029 Rev 6.1, 8/2/99
7

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Scalable VGA to NTSC/PAL Encoder

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