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부품번호 CH7006C 기능
기능 Digital PC to TV Encoder Features
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CH7006C 데이터시트, 핀배열, 회로
CHRONTEL
CH7006C
Digital PC to TV Encoder Features
Features
• Function compatible with CH7004
• Universal digital interface accepts YCrCb (CCIR601
or 656) or RGB (15, 16 or 24-bit) video data in both
non-interlaced and interlaced formats
• TrueScale TM rendering engine supports underscan
operations for various graphic resolutions† ¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
• Enhanced dot crawl control and area reduction
• Fully programmable through I2C port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Supports VBI pass-through
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin PLCC, 44-pin TQFP
Patent number 5,781,241
¥ Patent number 5,914,753
General Description
Chrontel’s CH7006 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. Suggested application use with the
Intel I740.* It provides a universal digital input port to
accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format.
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its TrueScaleTM
scaling and deflickering engine, the CH7006 supports full
vertical and horizontal underscan capability and operates
in 5 different resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7006 ideal for system-level
PC solutions. All features are software programmable
through a standard I2C port, to enable a complete PC
solution using a TV as the primary display.
LINE
MEMORY
YUV-RGB CONVERTER
D[15:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
I2C REGISTER &
CONTROL BLOCK
SYSTEM CLOCK
PLL
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
TIMING & SYNC
GENERATOR
Y/R
C/G
CVBS/B
RSET
SC SD
RESET*
XCLK
H V XI XO/FIN CSYNC P-OUT DS/BCO
Figure 1: Functional Block Diagram
201-0000-026 Rev 2.1, 8/2/99 *Intel I740 is a Trademark of Intel Corp.
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CH7006C pdf, 반도체, 판매, 대치품
CHRONTEL
Table 1. Pin Descriptions
44-Pin
PLCC
44Pin
TQFP
Type
4-10,
12-13,
15-21
1,2,
3,4,
6,7,9,
10,11,
12,13,
14,15,
42,43,
44
In
43 37 Out
1 39 In
3 41 In/Out
2 40 In/Out
41 35 In/Out
Symbol
D15-D0
P-OUT
XCLK
V
H
DS/BCO
CH7006C
Description
Digital Pixel Inputs
These pins accept digital pixel data streams with either 8, 12, or 16-bit
multiplexed or 16-bit non-multiplexed formats, determined by the input
mode setting (see Registers and Programming section). Inputs D0 - D7
are used when operating in 8-bit multiplexed mode. Inputs D0 - D11
are used when operating in 12-bit mode. Inputs D0 - D15 are used
when operating in 16-bit mode. The data structure and timing
sequence for each mode is described in the section on Digital Input
Port.
Pixel Clock Output
The CH7006, operating in master mode, provides a pixel data clocking
signal to the VGA controller. This clock will only be provided in master
clock modes and will be tri-stated otherwise. This pin provides the pixel
clock output signal (adjustable as 1X,2X or 3x) to the VGA controller
(see the section on Digital Video Interface, Registers and Programming
for more details). The capacitive loading on this pin should be kept to a
minimum.
Pixel Clock Input
To operate in a pure master mode, the P-OUT signal should be
connected to the XCLK input pin. To operate in a pseudo-master
mode, the P-OUT clock is used as a reference frequency, and a signal
locked to this output (at 1X, 1/2X, or 1/3X the P-OUT frequency) is input
to the XCLK pin. To operate in slave mode, the CH7006 accepts an
external pixel clock input at this pin. The capacitive loading on this pin
should be kept to a minimum.
Vertical Sync Input/Output
This pin accepts the vertical sync signal from the VGA controller, or
outputs a vertical sync to the VGA controller. The capacitive loading on
this pin should kept to a minimum.
Horizontal Sync Input/Output
This pin accepts the horizontal sync from the VGA controller, or outputs
a horizontal sync to the VGA controller. The capacitive loading on this
pin should be kept to a minimum.
Data/Start (input) / Buffered Clock (output)
When configured as an input, the rising edge of this signal identifies the
first active pixel of data for each active line.
When configured as an output this pin provides a buffered clock output.
The output clock can be selected using the BCO register (17h) (see
Registers and Programming).
38 32 In
XI Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be
attached between XI and XO/FIN. However, if an external CMOS clock
is attached to XO/FIN, XI should be connected to ground.
39 33 In XO/FIN Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN
and XI. An external CMOS compatible clock can be connected to
XO/FIN as an alternative.
4 201-0000-026 Rev 2.1, 8/2/99

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CH7006C 전자부품, 판매, 대치품
CHRONTEL
CH7006C
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7006 can operate in either master (the CH7004 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X,
or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7006
will automatically use both clock edges, if a multiplexed data format is selected.
Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7006. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may
also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, time
the first value of the (Total Pixels/line x Total Lines/Frame) column of Table 16 on page 31(Display Mode Register
00H description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical
sync signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of
Table 16 on page 31.)
Master Clock Mode: The CH7006 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock
signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the
pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC
transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet
the specified setup and hold times with respect to the pixel clock.
Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after
the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count),
plus horizontal sync width, will determine when the chip will begin to sample pixels.
Non-multiplexed Mode
In the 15/16-bit mode shown in Figure 4, the pixel data bus represents a 15/16-bit non-multiplexed data stream,
which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will
contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn
word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the
lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequence-
being set as Cb followed by Cr. The Cb and Cr data will be cosited with the Y value transmitted with the Cb value,
with the data sequence described in Table 3. The first active pixel is SAV pixels after the trailing edge of horizontal
sync, where SAV is a bus-controlled register.
201-0000-026 Rev 2.1, 8/2/99
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