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PDF K4D551638H Data sheet ( Hoja de datos )
| Número de pieza | K4D551638H | |
| Descripción | 256Mbit GDDR SDRAM | |
| Fabricantes | Samsung | |
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K4D551638H
256M GDDR SDRAM
256Mbit GDDR SDRAM
Revision 1.3
April 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.3 April 2007
1 page  
K4D551638H
256M GDDR SDRAM
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.CKE is synchronous
for Power down entry and exit, and for Self refresh entry. CKE is asynchronous for Self
refresh exit, and for output disable. CKE must be maintained high through Read and Write
accesses. Input buffers, excluding CK, CK and CKE are disbled during Power down. Input
buffers, excluding CKE are disabled during Self refresh. CKE is an SSTL_2 input, but will
detect a LVCMOS low level after Vdd is applied upon 1st power up. After Vref has become
stable during the power on and intialization sequence, it must be maintained for proper oper-
ation of the CKE receiver. For proper Self refresh entry and exit, Vref must be maintained to
this input.
CS enables the command decoder when low and disabled the command decoder when high.
CS
Input
When the command decoder is disabled, new commands are ignored but previous operations
continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with RAS low. Enables row
access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with CAS low. Enables col-
umn access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
LDQS,UDQS
Input/Output
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on
DQ8-DQ15.
LDM,UDM
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons
to the data on DQ8-DQ15.
DQ0 ~ DQ15
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A12
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev. 1.3 April 2007
5 Page 
K4D551638H
256M GDDR SDRAM
9.0 AC & DC OPERATING CONDITIONS
9.1 POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
VDD 2.35
2.6
2.7
V
1
Output Supply voltage
VDDQ
2.35
2.6
2.7
V
1
Reference voltage
VREF
0.49*VDDQ
-
0.51*VDDQ
V
2
Termination voltage
Vtt
VREF-0.04
VREF
VREF+0.04
V
3
Input logic high voltage
VIH(DC)
VREF+0.15
-
VDDQ+0.30
V
4
Input logic low voltage
VIL(DC)
-0.30
- VREF-0.15 V
5
Output logic high voltage
VOH
Vtt+0.76
-
-
V IOH=-15.2mA
Output logic low voltage VOL -
- Vtt-0.76 V IOL=+15.2mA
Input leakage current
IIL -5 - 5 uA
6
Output leakage current
IOL -5
-
5 uA
6
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF
may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
9.2 DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, (TA=0 to 65°C)
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current
in Power-down mode
Precharge Standby Current
in Non Power-down mode
Active Standby Current
power-down mode
Active Standby Current in
in Non Power-down mode
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Operating Current
(4Bank Interleaving)
Note :
1. Measured with output open.
2. Current meassured at VDD(max).
3. Refresh period is 64ms.
Symbol
Test Condition
ICC1
Burst Lenth=2 tRC ≥ tRC(min)
IOL=0mA, tCC= tCC(min)
ICC2P CKE ≤ VIL(max), tCC= tCC(min)
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
ICC3P CKE ≤ VIL(max), tCC= tCC(min)
ICC3N
ICC4
ICC5
ICC6
ICC7
CKE ≥ VIH(min), CS ≥ VIH(min),
tCC= tCC(min)
tRC ≥ tRFC(min)tRC ≥ tRFC(min)
Page Burst, All Banks activated.
tRC ≥ tRFC(min)
CKE ≤ 0.2V
Burst Length=4, tRC ≥ tRFC(min)
IOL=0mA, tCC = tCC(min)
- 11 -
Version
-40 -50
160 140
5
80 70
65 55
80 70
265 220
180 160
5
300 260
Unit Note
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2
mA 1, 2,3
mA 1, 2
mA 1, 2
Rev. 1.3 April 2007
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet K4D551638H.PDF ] | |
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