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부품번호 | K4D551638H-LC40 기능 |
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기능 | 256Mbit GDDR SDRAM | ||
제조업체 | Samsung | ||
로고 | |||
전체 18 페이지수
K4D551638H
256M GDDR SDRAM
256Mbit GDDR SDRAM
Revision 1.3
April 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.3 April 2007
K4D551638H
4.0 PIN CONFIGURATION (Top View)
256M GDDR SDRAM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 66 PIN TSOP(II) 57
11 (400mil x 875mil) 56
12 (0.65 mm Pin Pitch) 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
L(U)DQS
L(U)DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA0, BA1
A0 ~A12
DQ0 ~ DQ15
VDD
VSS
VDDQ
VSSQ
NC
VREF
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ’s
Ground for DQ’s
No Connection
Reference voltage
-4-
Rev. 1.3 April 2007
4페이지 K4D551638H
256M GDDR SDRAM
7.0 FUNCTIONAL DESCRIPTION
7.1 Power-Up Sequence
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and keep CKE at low state (All other inputs may be undefined)
- Apply VDD before VDDQ .
- Apply VDDQ before VREF & VTT
2. Start clock and maintain stable condition for minimum 200us.
3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high .
4. Issue precharge command for all banks of the device.
5. Issue a EMRS command to enable DLL
*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.
*1,2 7. Issue precharge command for all banks of the device.
8. Issue at least 2 or more auto-refresh commands.
9. Issue a mode register set command with A8 to low to initialize the mode register.
*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CK,CK
Command
precharge
ALL Banks
tRP
2 Clock min.
2 Clock min.
EMRS
MRS
DLL Reset
precharge
ALL Banks
tRP tRFC
1st Auto
Refresh
Inputs must be
stable for 200us
200 Clock min.
* When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
2nd Auto
Refresh
tRFC
2 Clock min.
Mode
Register Set
Any
Command
-7-
Rev. 1.3 April 2007
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부품번호 | 상세설명 및 기능 | 제조사 |
K4D551638H-LC40 | 256Mbit GDDR SDRAM | Samsung |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |