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CH7008A 데이터시트 PDF




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부품번호 CH7008A 기능
기능 Digital PC to TV Encoder Features
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CH7008A 데이터시트, 핀배열, 회로
CHRONTEL
CH7008A
Digital PC to TV Encoder Features
Features
• Support for low voltage interface to VGA controller
• Universal digital interface accepts YCrCb (CCIR656)
or RGB (15, 16 or 24-bit multiplexed) video data in
both non-interlaced and interlaced formats
• TrueScale TM rendering engine supports underscan
operations for various graphic resolutions† ¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
• Enhanced dot crawl control and area reduction
• Fully programmable through I2C port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin PLCC, 44-pin TQFP
General Description
Chrontel’s CH7008 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output on non-DVD enabled systems.
Suggested application use with the Intel 810 chipset &
Intel 810E chipset.* It provides a universal digital input
port to accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format.
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its TrueScaleTM
scaling and deflickering engine, the CH7008 supports full
vertical and horizontal underscan capability and operates
in 5 different resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7008 ideal for system-level
PC solutions. All features are software programmable
through a standard I2C port, to enable a complete PC
solution using a TV as the primary display.
Patent number 5,781,241
¥ Patent number 5,914,753
LINE
MEMORY
D[11:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
YUV-RGB CONVERTER
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
GPIO[1:0]
I2C REGISTER &
CONTROL BLOCK
SYSTEM CLOCK
PLL
TIMING & SYNC
GENERATOR
SC SD
RESET*
XCLK*
H V XI/FIN XO CSYNC P-OUT DS/BCO
Figure 1: Functional Block Diagram
201-0000-027 Rev 2.2, 9/30/99 *Intel 810 and Intel 810E are Trademarks of Intel Corp
Y/R
C/G
CVBS/B
ISET
1




CH7008A pdf, 반도체, 판매, 대치품
CHRONTEL
CH7008A
Table 1. Pin Descriptions
44-Pin
PLCC
1
44-Pin
TQFP
39
Type
In/Out
2 40 In
3 41 In
4 42 In/Out
Symbol
Description
VREF
XCLK
XCLK*
H
Reference Voltage Input
The VREF pin inputs a reference voltage of DVDD2/2. The signal is
derived externally through a resistor divider and decoupling capacitor,
and will be used as a reference level for data and sync inputs.
External Clock Input
This input along with XCLK* will form a differential clock input. For
applications where a differential clock is not available, the XCLK* pin
should be connected to the VREF pin.
External Clock Input*
See XCLK description
Horizontal Sync Input/Output
When the SYO bit is low, this pin accepts a horizontal sync input. The
level is 0 to DVDD2, with VREF as the threshold level.
When the SYO bit is high, the device will output a horizontal sync pulse.
The output is driven from the DVDD supply.
5
43 In/Out
V Vertical Sync Input/Output
When the SYO bit is low, this pin accepts a vertical sync input. The level
is 0 to DVDD2 with VREF as the threshold level.
6-10,12- 44,1-4,6-
13,15-19 7,9-13
20-21
14-15
23 17
26 20
27 21
28 22
30 24
In
In/Out
Out
Out
Out
Out
In
D[0]-D[11]
GPIO[0]
GPIO[1]
CSYNC
CVBS/B
C/G
Y/R
ISET
When the SYO bit is high, the device will output a vertical sync pulse.
The output is driven from the DVDD supply.
Data [0] through Data [11] Inputs
These pins accept 12 data inputs from the graphics controller. The level
is 0 to DVDD2, with VREF as the threshold level.
General Purpose Input/Output [0-1] and Internal pull-up
These pins provide general purpose I/O’s controlled via the IIC bus,
registers 1Bh and 1Ch, bits 7 and 6. The internal pull-up is to the DVDD
supply.
Composite Sync Output
A 75 termination resistor with short traces should be attached
between CSYNC and ground for optimum performance. In SCART
mode, this pin outputs the composite sync signal.
Composite Video Output/Blue Output
A 75 termination resistor with short traces should be attached
between CVBS and ground for optimum performance. In normal
operating modes other than SCART, this pin outputs the composite
video signal. In SCART mode, this pin outputs the blue signal.
Chroma Output/Green Output
A 75 termination resistor with short traces should be attached
between C and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the chroma video signal. In
SCART mode, this pin outputs the green signal.
Luma Output / Red Output
A 75 termination resistor with short traces should be attached
between Y and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the luma video signal. In
SCART mode, this pin outputs the red signal.
Current Set Resistor Input
This pin sets the DAC current. A 360 ohm resistor should be
connected between this pin and GND using short and wide traces.
4 201-0000-027 Rev 2.2, 9/30/99

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CH7008A 전자부품, 판매, 대치품
CHRONTEL
CH7008A
Input Data Formats
The XCLK and XCLK* signals are used to latch data from the graphics chip. Data can be latched coincident with
the rising edge of XCLK, falling edge of XCLK, or both edges, depending upon register settings of XCM and MCP.
The input data format is shown in Figure 4. The Pixel Data bus represents an 8 or 12-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. In IDF settings of 4, 5, 7, 8 and 9, the input data rate is 2X
pixel clock, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the
tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the lumi-
nance data, with the sequence being set as Cb0, Y0, Cr0, Y1 where Cb0,Y0,Cr0 refers to co-sited luminance and
color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards.
However, the clock frequency is dependent upon the current mode, not 27MHz, as specified in CCIR656.
HS
DS / BCO
XCLK(XCM=01)
XCLK*(XCM=01)
XCLK(XCM=00)
XCLK*(XCM=00)
SAV
(DSEN=0)
D[11:0]
P0a P0b P1a P1b P2a P2b
When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d.
Figure 4: Non-multiplexed Data Transfers
Table 3. RGB 8-bit Multiplexed Mode
IDF#
Format
Pixel#
Bus Data
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
7
RGB 5-6-5
P0b
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[5]
G0[4]
G0[3]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[5]
G1[4]
G1[3]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
8
RGB 5-5-5
P0b
x
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[4]
G0[3]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
x
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[4]
G1[3]
201-0000-027 Rev 2.2, 9/30/99
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CH7008A

Digital PC to TV Encoder Features

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