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11AA02E48 데이터시트 PDF




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11AA02E48 데이터시트, 핀배열, 회로
11AA02E48/11AA02E64
2K UNI/O® Serial EEPROMs with EUI-48or EUI-64Node Identity
Device Selection Table
Part Number
Density
(bits)
11AA02E48
11AA02E64
2K
2K
VCC Range
1.8V-5.5V
1.8V-5.5V
Page Size
(Bytes)
16
16
Temp.
Ranges
I
I
Packages
SN, TT
SN, TT
Node Address
EUI-48
EUI-64
Features
• Pre-Programmed Globally Unique, 48-Bit or
64-Bit Node Address
• Compatible with EUI-48and EUI-64
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 µA standby current, maximum
• 256 x 8-Bit Organization
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Maximum Bit Rate – Equivalent to
100 kHz Clock Frequency
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write Enable Latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4,000V
• 3-Lead SOT-23 and 8-Lead SOIC Packages
• Pb-Free and RoHS Compliant
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C
Description
The Microchip Technology Inc.
11AA02E48/11AA02E64 (11AA02EXX(1)) device is a
2 Kbit Serial Electrically Erasable PROM. The device is
organized in blocks of x8-bit memory and support the
patented(2) single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
Note 1: 11AA02EXX is used in this document as
a generic part number for the 11AA02E48
and 11AA02E64 devices.
2: Microchip’s UNI/O® Bus products are
covered by the following patents issued
in the U.S.A.: 7,376,020 and 7,788,430.
Low-voltage design permits operation down to 1.8V,
with standby and active currents of only 1 µA and
1 mA, respectively.
The 11AA02EXX is available in standard 8-lead
SOIC and 3-lead SOT-23 packages.
Package Types (not to scale)
3-Lead SOT-23
(TT)
VSS 3
2 VCC
1 SCIO
SOIC
(SN)
NC 1
NC 2
NC 3
VSS 4
8 VCC
7 NC
6 NC
5 SCIO
Pin Function Table
Name
Function
SCIO
VSS
VCC
Serial Clock, Data Input/Output
Ground
Supply Voltage
2008-2016 Microchip Technology Inc.
DS20002122D-page 1




11AA02E48 pdf, 반도체, 판매, 대치품
11AA02E48/11AA02E64
FIGURE 1-1:
10
SCIO
BUS TIMING – START HEADER
11 2
Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit
FIGURE 1-2:
SCIO
FIGURE 1-3:
SCIO
BUS TIMING – DATA
2
12
7
Data ‘0
Data ‘1
Data ‘1
BUS TIMING – STANDBY PULSE
9
8
Data ‘0
Standby
Mode
FIGURE 1-4:
BUS TIMING – JITTER
2
3
3
2
66
66
Ideal Edge
from Master
Ideal Edge
from Master
Ideal Edge
from Slave
Ideal Edge
from Slave
DS20002122D-page 4
2008-2016 Microchip Technology Inc.

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11AA02E48 전자부품, 판매, 대치품
11AA02E48/11AA02E64
3.3 Acknowledge
An Acknowledge routine occurs after each byte is
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
master, and the second bit is transmitted by the slave.
Note: A MAK must always be transmitted
following the start header.
The Master Acknowledge, or MAK, is signified by
transmitting a ‘1’, and informs the slave that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a
0’, and is used to end the current operation (and initiate
the write cycle for write operations).
Note:
When a NoMAK is used to end a WRITE or
WRSR instruction, the write cycle is not
initiated if no bytes of data have been
received.
The slave Acknowledge, or SAK, is also signified by
transmitting a ‘1’, and confirms proper communication.
However, unlike the NoMAK, the NoSAK is signified by
the lack of a middle edge during the bit period.
Note: In order to guard against bus contention, a
NoSAK will occur after the start header.
A NoSAK will occur for the following events:
• Following the start header
• Following the device address, if no slave on the
bus matches the transmitted address
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL, and ERAL during a write cycle.
• If the slave becomes out of sync with the master
• If a command is terminated prematurely by using
a NoMAK, with the exception of immediately after
the device address.
See Figure 3-3 and Figure 3-4 for details.
If a NoSAK is received from the slave after any byte
(except the start header), an error has occurred. The
master should then perform a standby pulse and begin
the desired command again.
FIGURE 3-3:
ACKNOWLEDGE
ROUTINE
Master
Slave
FIGURE 3-4:
MAK (‘1’)
ACKNOWLEDGE BITS
SAK (‘1’)
NoMAK (‘0’)
NoSAK(1)
Note 1: A NoSAK is defined as any sequence that is not a
valid SAK.
3.4 Device Addressing
A device address byte is the first byte received from the
master device following the start header. The device
address byte consists of a four-bit family code, for the
11AA02EXX this is set as ‘1010’. The last four bits of
the device address byte are the device code, which is
hardwired to ‘0000’.
FIGURE 3-5:
DEVICE ADDRESS BYTE
ALLOCATION
SLAVE ADDRESS
MAK SAK
10100000
3.5 Bus Conflict Protection
To help guard against high-current conditions arising
from bus conflicts, the 11AA02EXX features a
current-limited output driver. The IOL and IOH
specifications describe the maximum current that can
be sunk or sourced, respectively, by the SCIO pin. The
11AA02EXX will vary the output driver impedance to
ensure that the maximum current level is not exceeded.
MAK
SAK
2008-2016 Microchip Technology Inc.
DS20002122D-page 7

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