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부품번호 | UJA1065TW 기능 |
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기능 | High-speed CAN/LIN fail-safe system basis chip | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 30 페이지수
UJA1065
High-speed CAN/LIN fail-safe system basis chip
Rev. 07 — 25 February 2010
Product data sheet
1. General description
The UJA1065 fail-safe System Basis Chip (SBC) replaces basic discrete components that
are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN)
and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all
networking applications that control various power and sensor peripherals by using
high-speed CAN as the main network interface and LIN as a local sub-bus. The fail-safe
SBC contains the following integrated devices:
• High-speed CAN transceiver, interoperable and downward compatible with CAN
transceivers TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard
and the ISO 11898-5 standard (in preparation)
• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
• Advanced independent watchdog
• Dedicated voltage regulators for microcontroller and CAN transceiver
• Serial peripheral interface (full duplex)
• Local wake-up input port
• Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
• Advanced low-power concept
• Safe and controlled system start-up behavior
• Advanced fail-safe system behavior that prevents any conceivable deadlock
• Detailed status reporting on system and subsystem levels
The UJA1065 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is
always started up in a defined manner. In failure situations, the fail-safe SBC will maintain
microcontroller functionality for as long as possible to provide full monitoring and a
software-driven fall-back operation.
The UJA1065 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.
NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
3. Ordering information
Table 1. Ordering information
Type number[1] Package
Name
UJA1065TW
HTSSOP32
Description
Version
plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1
body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
[1] UJA1065TW/5V0 is for the 5 V version; UJA1065TW/3V3 is for the 3.3 V version.
4. Block diagram
SENSE
BAT42
BAT14
31
32
27
SYSINH
V3
INH/LIMP
29
30
17
INH
INTN
WAKE
TEST
SCK
SDI
SDO
SCS
7
18
WAKE
16
CHIP
TEMPERATURE
11
9
10 SPI
12
RTLIN
LIN
TXDL
RXDL
GND
26
25
3
5
23
Fig 1. Block diagram
BAT
MONITOR
V1
V2
UJA1065
4
V1
20
V2
SBC
FAIL-SAFE
SYSTEM
V1 MONITOR
RESET/EN
WATCHDOG
6 RSTN
8 EN
OSCILLATOR
GND SHIFT
DETECTOR
LIN
BAT42 BAT42
V2
HIGH
SPEED
CAN
24 SPLIT
21 CANH
22
CANL
13 TXDC
14 RXDC
001aac305
UJA1065_7
Product data sheet
Rev. 07 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
4 of 76
4페이지 NXP Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
6. Functional description
6.1 Introduction
The UJA1065 combines all peripheral functions around a microcontroller within typical
automotive networking applications into one dedicated chip. The functions are as follows:
• Power supply for the microcontroller
• Power supply for the CAN transceiver
• Switched BAT42 output
• System reset
• Watchdog with Window mode and Time-out mode
• On-chip oscillator
• High-speed CAN and LIN transceivers for serial communication; suitable for 14 V and
42 V applications
• SPI control interface
• Local wake-up input
• Inhibit or limp-home output
• System inhibit output port
• Compatibility with 42 V power supply systems
• Fail-safe behavior
6.2 Fail-safe system controller
The fail-safe system controller is the core of the UJA1065 and is supervised by a
watchdog timer that is clocked directly by the dedicated on-chip oscillator. The system
controller manages the register configuration and controls all internal functions of the
SBC. Detailed device status information is collected and presented to the microcontroller.
The system controller also provides the reset and interrupt signals.
The fail-safe system controller is a state machine. The different operating modes and the
transitions between these modes are illustrated in Figure 3. The following sections give
further details about the SBC operating modes.
UJA1065_7
Product data sheet
Rev. 07 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |