|
|
|
부품번호 | UJA1069TW 기능 |
|
|
기능 | LIN fail-safe system basis chip | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 30 페이지수
UJA1069
LIN fail-safe system basis chip
Rev. 04 — 28 October 2009
Product data sheet
1. General description
The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components
which are common in every Electronic Control Unit (ECU) with a Local Interconnect
Network (LIN) interface. The fail-safe SBC supports all networking applications which
control various power and sensor peripherals by using LIN as a local sub-bus. The
fail-safe SBC contains the following integrated devices:
• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
• Advanced independent watchdog
• Dedicated voltage regulator for microcontroller
• Serial peripheral interface (full duplex)
• Local wake-up input port
• Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
• Advanced low-power concept
• Safe and controlled system start-up behavior
• Advanced fail-safe system behavior that prevents any conceivable deadlock
• Detailed status reporting on system and sub-system levels
The UJA1069 is designed to be used in combination with a microcontroller and a LIN
controller. The fail-safe SBC ensures that the microcontroller is always started up in a
defined manner. In failure situations the fail-safe SBC will maintain the microcontroller
function for as long as possible, to provide full monitoring and software driven fall-back
operation.
The UJA1069 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.
NXP Semiconductors
4. Block diagram
UJA1069
LIN fail-safe system basis chip
SENSE
BAT42
BAT14
31 (23)
32 (24)
27 (19)
SYSINH
V3
INH/LIMP
29 (21)
30 (22)
17 (13)
INH
INTN
WAKE
TEST
SCK
SDI
SDO
SCS
7 (6)
18 (14)
16 (12)
WAKE
CHIP
TEMPERATURE
11 (10)
9 (8)
10 (9)
SPI
12 (11)
RTLIN
LIN
TXDL
RXDL
GND
26 (18)
25 (17)
3 (2)
5 (4)
23 (15)
BAT
MONITOR
V1
SBC
FAIL-SAFE
SYSTEM
LIN
BAT42
The pin numbers in parenthesis are for the UJA1069TW24 version.
Fig 1. Block diagram
UJA1069
(3) 4
V1
V1 MONITOR
RESET/EN
(5) 6
(7) 8
RSTN
EN
WATCHDOG
OSCILLATOR
001aad669
UJA1069_4
Product data sheet
Rev. 04 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
4 of 64
4페이지 NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Table 2.
Symbol
V3
SENSE
BAT42
Pin description …continued
Pin Description
HTSSOP32 HTSSOP24
30 22 unregulated 42 V output (BAT42 related; continuous
output, or cyclic mode synchronized with local wake-up
input)
31 23 fast battery interrupt / chatter detector input
32 24 42 V battery supply input (connect this pin to BAT14 in
14 V applications)
The exposed die pad at the bottom of the package allows better dissipation of heat from
the SBC via the printed-circuit board. The exposed die pad is not connected to any active
part of the IC and can be left floating, or can be connected to GND for the best EMC
performance.
6. Functional description
6.1 Introduction
The UJA1069 combines all peripheral functions around a microcontroller within typical
automotive networking applications into one dedicated chip. The functions are as follows:
• Power supply for the microcontroller
• Switched BAT42 output
• System reset
• Watchdog with Window mode and Time-out mode
• On-chip oscillator
• LIN transceiver for serial communication
• SPI control interface
• Local wake-up input
• Inhibit or limp-home output
• System inhibit output port
• Compatibility with 42 V power supply systems
• Fail-safe behavior
6.2 Fail-safe system controller
The fail-safe system controller is the core of the UJA1069 and is supervised by a
watchdog timer which is clocked directly by the dedicated on-chip oscillator. The system
controller manages the register configuration and controls all internal functions of the
SBC. Detailed device status information is collected and presented to the microcontroller.
The system controller also provides the reset and interrupt signals.
The fail-safe system controller is a state machine. The different operating modes and the
transitions between these modes are illustrated in Figure 4. The following sections give
further details about the SBC operating modes.
UJA1069_4
Product data sheet
Rev. 04 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
7 of 64
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ UJA1069TW.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
UJA1069TW | LIN fail-safe system basis chip | NXP Semiconductors |
UJA1069TW24 | LIN fail-safe system basis chip | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |