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부품번호 | UJA1079TW 기능 |
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기능 | LIN core system basis chip | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 30 페이지수
UJA1079
LIN core system basis chip
Rev. 02 — 27 May 2010
Product data sheet
1. General description
The UJA1079 core System Basis Chip (SBC) replaces the basic discrete components
commonly found in Electronic Control Units (ECU) with a Local Interconnect Network
(LIN) interface.
The UJA1079 supports the networking applications used to control power and sensor
peripherals by using the LIN interface as a local sub-bus.
The core SBC contains the following integrated devices:
• LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with
LIN 1.3
• Advanced independent watchdog (UJA1079/xx/WD versions)
• 250 mA voltage regulator for supplying a microcontroller; extendable with external
PNP transistor for increased current capability and dissipation distribution
• Serial Peripheral Pnterface (SPI) (full duplex)
• 2 local wake-up input ports
• Limp home output port
In addition to the advantages gained from integrating these common ECU functions in a
single package, the core SBC offers an intelligent combination of system-specific
functions such as:
• Advanced low-power concept
• Safe and controlled system start-up behavior
• Detailed status reporting on system and sub-system levels
The UJA1079 is designed to be used in combination with a microcontroller. The SBC
ensures that the microcontroller always starts up in a controlled manner.
NXP Semiconductors
4. Block diagram
BAT
GND
SCK
SDI
SDO
SCSN
WAKE1
WAKE2
WDOFF
EN
DLIN
LIN
TXDL
RXDL
WAKE
BAT
V1
V1
UV
SYSTEM
CONTROLLER
LIN BAT
Fig 1. Block diagram
UJA1079
LIN core system basis chip
UJA1079
V1
EXT. PNP
CTRL
OSC
TEMP
VEXCTRL
VEXCC
WBIAS
INTN
RSTN
LIMP
015aaa123
UJA1079_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
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4페이지 NXP Semiconductors
UJA1079
LIN core system basis chip
The system controller is a state machine. The SBC operating modes, and how transitions
between modes are triggered, are illustrated in Figure 3. These modes are discussed in
more detail in the following sections.
UJA1079_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
7 of 45
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UJA1079TW | LIN core system basis chip | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |