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부품번호 UJA1164TK 기능
기능 Mini high-speed CAN system basis chip
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UJA1164TK 데이터시트, 핀배열, 회로
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Rev. 2 — 17 April 2014
Product data sheet
1. General description
The UJA1164 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a
microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The
UJA1164 can be operated in a very low-current Standby mode with bus wake-up
capability and supports ISO 11898-6 compliant autonomous CAN biasing.
The UJA1164 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898
including CAN FD, additional timing parameters defining loop delay symmetry are
included. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to
be adapted for use in a specific application. This makes it possible to configure the
power-on behavior of the UJA1164 to meet the requirements of different applications.
2. Features and benefits
2.1 General
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability




UJA1164TK pdf, 반도체, 판매, 대치품
NXP Semiconductors
5. Pinning information
5.1 Pinning
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
terminal 1
index area
TXD 1
14 SCSN
GND 2
13 CANH
V1 3
12 CANL
RXD 4
UJA1164
11 SDI
RSTN 5
10 BAT
SDO 6
9 i.c.
i.c. 7
8 SCK
015aaa441
Transparent top view
Fig 2. Pin configuration diagram
5.2 Pin description
Table 2.
Symbol
TXD
GND
V1
RXD
RSTN
SDO
i.c.
SCK
i.c.
BAT
SDI
CANL
CANH
SCSN
Pin description
Pin Description
1 transmit data input
2[1] ground
3 5 V microcontroller supply voltage
4 receive data output; reads out data from the bus lines
5 reset input/output
6 SPI data output
7 internally connected; should be left floating or connected to GND
8 SPI clock input
9 internally connected; should be left floating or connected to GND
10 battery supply voltage
11 SPI data input
12 LOW-level CAN bus line
13 HIGH-level CAN bus line
14 SPI chip select input
[1] The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the
SBC via the printed circuit board. For enhanced thermal and electrical performance, it is recommended to
solder the exposed die pad to GND.
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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UJA1164TK 전자부품, 판매, 대치품
NXP Semiconductors
UJA1164
Mini high-speed CAN system basis chip with Standby mode &
watchdog
After the UJA1164 exits Reset mode (positive edge on RSTN), an SPI read/write access
must not be attempted for at least tto(SPI). Any earlier access may be ignored (without
generating an SPI failure event).
6.1.1.4 Off mode
The UJA1164 switches to Off mode when the battery is first connected or from any mode
when VBAT < Vth(det)poff. Only power-on detection is enabled; all other modules are
inactive. The UJA1164 starts to boot up when the battery voltage rises above the
power-on detection threshold Vth(det)pon (triggering an initialization process) and switches
to Reset mode after tstartup. In Off mode, the CAN pins disengage from the bus (zero load;
high-ohmic).
6.1.1.5 Overtemp mode
Overtemp mode is provided to prevent the UJA1164 being damaged by excessive
temperatures. The UJA1164 switches immediately to Overtemp mode from any mode
(other than Off mode) when the global chip temperature rises above the overtemperature
protection activation threshold, Tth(act)otp.
To help prevent the loss of data due to overheating, the UJA1164 issues a warning when
the IC temperature rises above the overtemperature warning threshold (Tth(warn)otp). When
this happens, status bit OTWS is set and an overtemperature warning event is captured
(OTW = 1), if enabled (OTWE = 1).
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD, which will persist after the overtemperature
event has been cleared. V1 is off and pin RSTN is driven LOW after td(uvd)V1.
The UJA1164 exits Overtemp mode:
and switches to Reset mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
if the device is forced to switch to Off mode (VBAT < Vth(det)poff)
6.1.1.6 Forced Normal mode
Forced Normal mode simplifies SBC testing and is useful for initial prototyping and failure
detection, as well as first flashing of the microcontroller. The watchdog is disabled in
Forced Normal mode. The low-drop voltage regulator (V1) and the CAN transceiver are
active.
Bit FNMC is factory preset to 1, so the UJA1164 initially boots up in Forced Normal mode
(see Table 8). This allows a newly installed device to be run in Normal mode without a
watchdog. So the microcontroller can be flashed via the CAN bus in the knowledge that a
watchdog timer overflow will not trigger a system reset.
The register containing bit FNMC (address 74h) is stored in non-volatile memory (see
Section 6.9). So once bit FNMC is programmed to 0, the SBC will no longer boot up in
Forced Normal mode, allowing the watchdog to be enabled.
UJA1164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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UJA1164TK

Mini high-speed CAN system basis chip

NXP Semiconductors
NXP Semiconductors

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