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UJA1061TW 데이터시트 PDF




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부품번호 UJA1061TW 기능
기능 Low speed CAN/LIN system basis chip
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UJA1061TW 데이터시트, 핀배열, 회로
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DATA SHEET
UJA1061
Low speed CAN/LIN system
basis chip
Objective specification
2004 Mar 22




UJA1061TW pdf, 반도체, 판매, 대치품
Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
1.4 CAN physical layer
ISO11898-3 compliant fault-tolerant CAN transceiver
Downwards compatible with TJA1054/TJA1054A
Enhanced error signalling and reporting
Separated low-drop-out voltage regulator for CAN bus:
– Microcontroller supply independent, autonomous
physical layer bus failure management
– Significantly improves EMC performance
Partial networking capability:
– Completely passive behaviour to the bus when
unpowered
– Selective Sleep option with global wake-up allowing
selected CAN bus communication without waking-up
sleeping nodes.
1.5 LIN physical layer
LIN2.0 compatible LIN transceiver
Enhanced error signalling and reporting.
2 GENERAL DESCRIPTION
The UJA1061 is a System Basis Chip (SBC), replacing
basic discrete components that are commonly used in
Electronic Control Units (ECUs) for automotive body
multiplexing. The UJA1061 supports any body application
which controls various power peripherals by using the
fault-tolerant CAN as the main physical layer and the LIN
physical layer as local sub-bus. The UJA1061 contains the
following integrated devices:
Low speed, fault-tolerant CAN transceiver,
inter-operable and downwards compatible with CAN
transceivers TJA1054 and TJA1054A, and compatible
with ISO11898-3 standard
LIN transceiver compatible with LIN specification,
revision 2.0
Watchdog
Separate voltage regulators for both host controller and
CAN transceiver
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit output port.
In addition to the cost advantages compared with
conventional multi-chip solutions, the UJA1061 offers an
intelligent combination of system-specific functions such
as:
Advanced low power concept
Safe and controlled system start-up behaviour
Advanced fail-safe system behaviour that prevents any
deadlock
Detailed status reporting on system and sub-system (for
example, CAN) levels.
The UJA1061 is intended to be used in combination with a
microcontroller and a CAN controller. The microcontroller
is the first to come and the last to go in an ECU designed
with the UJA1061. In failure situations, the UJA1061
maintains the microcontroller function as long as possible
in order to provide full monitoring and software driven
fall-back operation.
The UJA1061 can be operated in:
Single 42 V power supply architecture when combined
with an external step-down converter
Single 14 V power supply architecture
Dual 14 V and 42 V power supply architecture.
3 ORDERING INFORMATION
TYPE
NUMBER(1)
UJA1061TW/*
NAME
HTSSOP32
PACKAGE
DESCRIPTION
plastic thermal enhanced thin shrink small outline package;
32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad
Note
1. Add suffix to indicate version:
* = 5V0 for 5 V version
* = 3V3 for 3.3 V version
* = 3V0 for 3 V version
* = 2V5 for 2.5 V version.
VERSION
SOT549-1
2004 Mar 22
4

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UJA1061TW 전자부품, 판매, 대치품
Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
SYMBOL
SYSINH
V3
SENSE
BAT42
PIN DESCRIPTION
29 42 V inhibit (controlling an external 42 V to 14 V DC-to-DC converter, for example)
30 unregulated 42 V supply output, Continuous and Cyclic modes for supply of
wake-up switches, Cyclic mode synchronized with local WAKE input ports
31 fast battery interrupt/chatter detector input
32 42 V battery supply input; protected up to 60 V
n.c. 1
n.c. 2
TXDL 3
V1 4
RXDL 5
RSTN 6
INTN 7
EN 8
SDI 9
SDO 10
SCK 11
SCS 12
TXDC 13
RXDC 14
n.c. 15
TEST 16
UJA1061
32 BAT42
31 SENSE
30 V3
29 SYSINH
28 n.c.
27 BAT14
26 RTLIN
25 LIN
24 RTH
23 GND
22 CANL
21 CANH
20 V2
19 RTL
18 WAKE
17 INH/LIMP
mce623
Fig.2 Pin configuration.
2004 Mar 22
7

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