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HV100K5-G 데이터시트 PDF




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부품번호 HV100K5-G 기능
기능 Inrush Current Limiter Controllers
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HV100K5-G 데이터시트, 핀배열, 회로
Supertex inc.
HV100
3-Pin Hotswap, Inrush Current Limiter Controllers
(Negative Supply Rail)
Features
►Pass element is only external part
►No sense resistor required
►Auto-adapt to pass element
►Short circuit protection
►UV & POR supervisory circuits
►2.5s auto retry
►±10V to ±72V input voltage range
►0.6mA typical operating supply current
►Built in clamp for AC path turn-on glitch
Applications
►-48V central office switching (line cards)
+48V server networks
+48V storage area networks
+48V peripherals, routers, switches
+24V cellular and fixed wireless (bay stations,
line cards)
►+24V industrial systems
►+24V UPS systems
-48V PBX & ADSL systems (line cards)
Distributed power systems
Powered ethernet for VoIP
General Description
The HV100 is a 3-pin hotswap controller available in the
SOT-223 package, which requires no external components
other than a pass element.
The HV100 contains many of the features found in hotswap
controllers with 8 pins or more, and which generally require
many external components. These features include undervolt-
age (UV) detection circuits, power on reset (POR) supervisory
circuits, inrush current limiting, short circuit protection, and
auto-retry. In addition, the HV100 uses a patent pending
mechanism to sample and adapt to any pass element, result-
ing in consistent hotswap profiles without any programming.
Typical Application Circuit
GND
VPP
GATE
VNN
400µF
DC/DC
Converter
+5.0V
COM
HV100
-48V
IRF530
Doc.# DSFP-HV100
B060513
Supertex inc.
www.supertex.com




HV100K5-G pdf, 반도체, 판매, 대치품
HV100
Functional Description
Insertion into Hot Backplanes
Telecom, data network and some computer applications
require the ability to insert and remove circuit cards from
systems without powering down the entire system. Since all
circuit cards have some filter capacitance on the power rails,
which is especially true in circuit cards or network terminal
equipment utilizing distributed power systems, the insertion
can result in high inrush currents that can cause damage to
connector and circuit cards and may result in unacceptable
disturbances on the system backplane power rails.
The HV100 is designed to facilitate the insertion and removal
of these circuit cards or connection of terminal equipment
by eliminating these inrush currents and powering up these
circuits in a controlled manner after full connector insertion
has been achieved. The HV100 is intended to provide this
control function on the negative supply rail.
Description of Operation
On initial power application the high input voltage internal
regulator seeks to provide a regulated supply for the internal
circuitry. Until the proper internal voltage is achieved all circuits
are held reset by the internal UVLO and the GATE to source
voltage of the external N-channel MOSFET is held off. Once
the internal regulator voltage exceeds the UVLO threshold,
the input undervoltage detection circuit (UV) senses the input
voltage to confirm that it is above the internally programmed
threshold. If at any time the input voltage falls below the UV
threshold, all internal circuitry is reset and the GATE output
is pulled down to VNN. UVLO detection works in conjunction
with a power on reset (POR) timer of approximately 3.5ms to
overcome contact bounce. Once the UVLO is satisfied, the
GATE is held to VNN until a POR timer expires. Should the UV
monitor toggle before the POR timer expires, the POR timer
will be reset. This process will be repeated each time UVLO
is satisfied until a full POR period has been achieved.
After completion of a full POR period, the MOSFET GATE auto-
adapt operation begins. A reference current source is turned
on which begins to charge an internal capacitor generating
a ramp voltage which rises at a slew rate of 2.5V/ms. This
reference slew rate is used by a closed loop system to gener-
ate a GATE output current to drive the GATE of the external
N-channel MOSFET with a slew rate that matches the refer-
ence slew rate. Before the GATE crosses a reference voltage,
which is well below the VTH of industry standard MOSFETs,
the pull-up current value is stored and the auto-adapt loop
is opened. This stored pull-up current value is used to drive
the GATE during the remainder of the hotswap period. The
result is a normalization with CISS , which for most MOSFETs
scales with CRSS.
The MOSFET GATE is charged with a current source until
it reaches its turn on threshold and starts to charge the load
capacitor. At this point the onset of the Miller Effect causes
the effective capacitance looking into the GATE to rise, and
the current source charging the GATE will have little effect
on the GATE voltage. The GATE voltage remains essentially
constant until the output capacitor is fully charged.At this point
the voltage on the GATE of the MOSFET continues to rise to
a voltage level that guarantees full turn on of the MOSFET.
It will remain in the full on state until an input under voltage
condition is detected.
If the circuit attempts turn on into a shorted load, then the Miller
Effect will not occur. The GATE voltage will continue to rise
essentially at the same rate as the reference ramp indicating
that a short circuit exists. This is detected by the control circuit
and results in turning off the MOSFET initiating a 2.5 second
delay, after which a normal restart is attempted.
If at any time during the start up cycle or thereafter, the input
voltage falls below the UV threshold the GATE output will
be pulled down to VNN, turning off the N-channel MOSFET
and all internal circuitry is reset. A normal restart sequence
will be initiated once the input voltage rises above the UVLO
threshold plus hysteresis.
Doc.# DSFP-HV100
B060513
Supertex inc.
4 www.supertex.com

4페이지










HV100K5-G 전자부품, 판매, 대치품
Implementing PWRGD Control
Due to the HV100’s small footprint, it is possible to create an
open drain PWRGD signal using external components and
still maintain a size comparable with the smallest hotswap
controllers available elsewhere. To accomplish this an ex-
ternal MOSFET may be used in conjunction with the GATE
output. Simply use a high impedance divider (10MΩ) sized
so that the open drain PWRGD MOSFET threshold will only
be reached once the HV100’s GATE voltage rises well above
the current limit value required by the external MOSFET pass
device. Alternatively a Zener diode between the GATE output
and the PWRGD MOSFET GATE set at a voltage higher than
the maximum pass element Vt will also work.
Functional Block Diagram
VPP Regulator
UVLO
UV
POR
Timer
Restart
Timer
Reference
Generator
Logic
HV100
HV100
PWGRD
GATE
VNN
Doc.# DSFP-HV100
B060513
Supertex inc.
7 www.supertex.com

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관련 데이터시트

부품번호상세설명 및 기능제조사
HV100K5-G

Inrush Current Limiter Controllers

Supertex
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