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PDF HV232PJ-G Data sheet ( Hoja de datos )
| Número de pieza | HV232PJ-G | |
| Descripción | Low Charge Injection 8-Channel High Voltage Analog Switch | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Supertex inc.
Low Charge Injection 8-Channel High Voltage
Analog Switches with Bleed Resistors
HV232
Features
►►HVCMOS® technology for high performance
►►Very low quiescent power dissipation (10µA max.)
►►Output on-resistance (22Ω typ.)
►►Integrated bleed resistors on the outputs
►►Low parasitic capacitances
►►DC to 50MHz small signal frequency response
►►-60dB typical output off isolation at 5.0MHz
►►CMOS logic circuitry for low power
►►Excellent noise immunity
►►On-chip shift register, latch and clear logic circuitry
►►Flexible high voltage supplies
Applications
►► Medical ultrasound imaging
►► Piezoelectric transducer drivers
General Description
The Supertex HV232 is a low charge injection 8-channel,
high-voltage, analog switch integrated circuit (IC) with bleed
resistors. This device can be used in applications requiring
high voltage switching controlled by low voltage control
signals, such as ultrasound imaging and printers. The bleed
resistors eliminate voltage built up on capacitive loads such
as piezoelectric transducers. Input data is shifted into an 8-bit
shift register which can then be retained in an 8-bit latch. To
reduce any possible clock feed-through noise, Latch Enable
(LE) should be left high until all bits are clocked in. Using
HVCMOS® technology, this switch combines high voltage
bilateral DMOS switches and low power CMOS logic to
provide efficient control of high voltage analog signals.
This IC is suitable for various combinations of high voltage
supplies, e.g., VPP/VNN: +50V/–150V, or +100V/–100V.
Block Diagram
Latches
D
LE
CL
Level
Shifters
Output
Switches
SW0
D
LE SW1
CL
DIN
8-Bit
CLK Shift
Register
DOUT
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
SW2
SW3
SW4
SW5
D
LE SW6
CL
D
LE SW7
CL
Doc.# DSFP-HV232
C071613
VDD
LE CL
VNN VPP
RGND
Supertex inc.
www.supertex.com
1 page  
HV232
Truth Table
D0 D1 D2 D3 D4 D5 D6 D7 LE CLK SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L L L Off
H L L On
L
LL
Off
H
LL
On
L
LL
Off
H
LL
On
L
LL
Off
H
LL
On
L LL
Off
H LL
On
L LL
Off
H LL
On
L LL
Off
H LL
On
LLL
Off
HLL
On
XXXXXXXXH L
Hold Previous State
XXXXXXXXXH
All Switches Off
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. DOUT is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DN+1
DN
DATA
IN
50%
50%
DN-1
Doc.# DSFP-HV232
C071613
LE
CLOCK
DATA
OUT
VOUT OFF
(typ)
ON
CLR
50%
50%
tSU
50%
tWLE
tSD
50%
th
tDO
50%
tOFF
90%
50%
tWCL
5
50%
tON
10%
Supertex inc.
www.supertex.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HV232PJ-G.PDF ] | |
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