|
|
PDF KAF-0261 Data sheet ( Hoja de datos )
| Número de pieza | KAF-0261 | |
| Descripción | CCD Image Sensor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de KAF-0261 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
KAF-0261
512 (H) x 512 (V) Full Frame
CCD Image Sensor
Description
The KAF−0261 Image Sensor is a high performance, charge
coupled device (CCD) designed for a wide range of image sensing
applications.
The sensor incorporates true two−phase CCD technology,
simplifying the support circuits required to drive the sensor as well as
reducing dark current without compromising charge capacity. The
sensor also utilizes a transparent gate electrode to improve sensitivity
compared to the use of a standard front side illuminated polysilicon
electrode.
Selectable on−chip output amplifiers allow operation to be
optimized for different imaging needs: Low Noise (when using the
high−sensitivity output) or Maximum Dynamic Range (when using
the low−sensitivity output).
The low dark current of the KAF−0261 makes this device suitable
for low light imaging applications without sacrificing charge capacity.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Full Frame CCD
Number of Active Pixels
512 (H) x 512 (V)
Pixel Size
20 mm (H) x 20 mm (V)
Active Image Size
10.2 mm (H) x 10.2 mm (V)
Chip Size
11.3 mm (H) x 11.6 mm (V)
Optical Fill Factor
100%
Output Sensitivity
High Sensitivity Output
High Dynamic Range Output
10 mV/electron
2.0 mV/electron
Saturation Signal
High Sensitivity Output
High Dynamic Range
200,000 electrons
500,000 electrons
Readout Noise (1 MHz)
Dark Current
(25°C, Accumulation Mode)
22 electrons rms
< 30 pA/cm3
Dark Current Doubling Rate
Dynamic Range (Sat Sig/Dark Noise)
High Sensitivity Output
6°C
83 dB
High Dynamic Range Output Range
87 dB
Quantum Efficiency (450, 550, 650 nm) 35%, 55%, 58%
Maximum Data Rate
High Sensitivity Output
High Dynamic Range Output
5 MHz
2 MHz
Transfer Efficiency
> 0.99997
Package
CERDIP Package
Cover Glass
Clear or AR coated, 2 sides
www.onsemi.com
Figure 1. KAF−0261 CCD Image Sensor
Features
• True Two Phase Full Frame Architecture
• Transparent Gate Electrode for High
Sensitivity
• 100% Fill Factor
• Low Dark Current
• User−selectable Outputs Allow either Low
Noise or High Dynamic Range Operation
• Single Readout Register
• These Devices are Pb−Free and are RoHS
Compliant
Applications
• Scientific Imaging
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 3
1
Publication Order Number:
KAF−0261/D
1 page  
KAF−0261
DEVICE DESCRIPTION
Pin Description and Device Orientation
OG 1
VOUT2 2
VDD1/VDD2 3
VRD 4
φR 5
VSS 6
φH1 7
φH2 8
VOUT1 9
φH21 10
φH22 11
N/C 12
Pixel (1,1)
Pixel (512,512)
Figure 4. Pinout Diagram
24 VLG
23 GUARD
22 φV1
21 φV1
20 φV2
19 φV2
18 φV2
17 φV2
16 φV1
15 φV1
14 SUB
13 SUB
Table 3. PIN DESCRIPTION
Pin Name
Description
1 OG Output Gate
2 VOUT2 Video Output from High Sensitivity Two−
Stage
3 VDD1 / Amplifier Supply for VOUT1 and VOUT2
VDD2
Amplifiers
4
VRD
Reset Drain
5 fR Reset Clock
6
VSS
Output Amplifier Return
7 fH1 Horizontal (Serial) CCD Clock − Phase 1
8 fH2 Horizontal (Serial) CCD Clock − Phase 2
9 VOUT1 Video Output from High Dynamic Range
Single−Stage Amplifier
10 fH21 Last Horizontal (Serial) CCD Phase −
Split Gate
11 fH22 Last Horizontal (Serial) CCD Phase −
Split Gate
12 N/C
No Connection
13 VSUB Substrate
14 VSUB Substrate
15 fV1 Vertical (Parallel) CCD Clock − Phase 1
16 fV1 Vertical (Parallel) CCD Clock − Phase 1
17 fV2 Vertical (Parallel) CCD Clock − Phase 2
18 fV2 Vertical (Parallel) CCD Clock − Phase 2
19 fV2 Vertical (Parallel) CCD Clock − Phase 2
20 fV2 Vertical (Parallel) CCD Clock − Phase 2
21 fV1 Vertical (Parallel) CCD Clock − Phase 1
22 fV1 Vertical (Parallel) CCD Clock − Phase 1
23 GUARD Guard Ring
24 VLG First Stage Load Transistor Gate for
Two−Stage
1. Pins 15, 16, 21, and 22 must be connected together − only one
Phase 1−clock driver is required.
2. Pins 17, 18, 19, and 20 must be connected together − only one
Phase 2−clock driver is required.
www.onsemi.com
5
5 Page 
Normal Readout Timing
ö V1
ö V2
ö H1
ö H2
tint
Line
KAF−0261
Frame Timing
tReadout
1 Frame = 520 Lines
12
520
520
Line Timing Detail
1 line
V1
töV
töV
V2
töHS 1(tpix)
H1
H2
530 counts
R
Line Content
1−4 5−8
9 − 520
Photoactive Pixels
Dark Reference Pixels
521−528 529−530
Dummy Pixels
öR
öH1
öH2
Vout
Pixel Timing Detail
töR
tpix 1 count
Vsat
Vdark
Vpix
Vodc
Vsub
V sat
V dark
V pix
V odc
V sub
Saturated pixel video output signal
Video output signal in no light situation, not zero due to Jdark
Pixel video output signal level, more electrons =more negative*
Video level offset with respect to vsub
Analog Ground
* See Image Aquisition section
Figure 7. Timing Diagrams
NOTE: This device is suitable for a wide range of applications requiring a variety of different timing frequencies.
Therefore, only maximum and minimum values are shown above. Consult ON Semiconductor in those
situations, which require special consideration.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet KAF-0261.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| KAF-0261 | CCD Image Sensor | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |