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KAF-1001 데이터시트 PDF




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기능 CCD IMAGE SENSOR
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KAF-1001 데이터시트, 핀배열, 회로
KAF-1001 IMAGE SENSOR
1024 (H) X 1024 (V) FULL FRAME CCD IMAGE SENSOR
JUNE 18, 2014
DEVICE PERFORMANCE SPECIFICATION
REVISION 1.1 PS-0033




KAF-1001 pdf, 반도체, 판매, 대치품
KAF-1001 Image Sensor
Summary Specification
KAF-1001 Image Sensor
DESCRIPTION
The KAF-1001 Image Sensor is a high-performance
charge-coupled device (CCD) designed for a wide range
of image sensing applications.
The sensor incorporates true two-phase CCD technology,
simplifying the support circuits required to drive the
sensor as well as reducing dark current without
compromising charge capacity. The sensor also utilizes
the TRUESENSE Transparent Gate Electrode to improve
sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
Selectable on-chip output amplifiers allow operation to
be optimized for different imaging needs: Low Noise
(when using the high-sensitivity output) or Maximum
Dynamic Range (when using the low-sensitivity output).
FEATURES
True Two Phase Full Frame Architecture
TRUESENSE Transparent Gate Electrode for high
sensitivity
100% Fill Factor
Low Dark Current
Single Readout Register
User-selectable outputs allow either Low Noise
or High Dynamic Range operation
APPLICATIONS
Scientific
Medical
Parameter
Architecture
Pixel Count
Pixel Size
Active Image Size
Chip Size
Optical Fill-Factor
Saturation Signal
High Sensitivity Output
High Dynamic Range
Output Sensitivity
High Sensitivity Output
High Dynamic Range
Readout Noise (1 MHz)
Dark Current
(25 °C, Accumulation Mode)
Dark Current Doubling Rate
Dynamic Range (Sat Sig/Dark Noise)
High Sensitivity Output
High Dynamic Range
Quantum Efficiency
(450, 550, 650 nm)
Maximum Data Rate
High Sensitivity Output
High Dynamic Range
Transfer Efficiency (2 MHz, to 40 °C)
Package
Cover Glass
Typical Value
Full Frame CCD
1024 (H) x 1024 (V)
24 µm (H) x 24 µm (V)
24.6 mm (H) x 24.6 mm (V)
28.6 mm (H) x 25.5 mm (V)
100%
240,000 electrons
650,000 electrons
11 µV/electron
2 µV/electron
15 electrons rms
<30 pA/cm2
56 °C
83 dB
97 dB
40%, 55%, 65%
5 MHz
2 MHz
>0.99997
CERDIP Package (sidebrazed)
Clear
www.truesenseimaging.com
Revision 1.1 PS-0033 Pg 4

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KAF-1001 전자부품, 판매, 대치품
KAF-1001 Image Sensor
H2
H1 HCCD
Charge
H2 Transfer
H1L VDD
Vog
R
Vrd
Floating
Diffusion
Vout
Vlg
Source
Follower
#1
Figure 2: Output Schematic
Source
Follower
#2
IMAGE ACQUISITION
An image is acquired when incident light, in the form of photons, falls on the array of pixels in the vertical CCD register
and creates electron-hole pairs (or simply electrons) within the silicon substrate. This charge is collected locally by the
formation of potential wells created at each pixel site by induced voltages on the vertical register clock lines (φV1,
φV2). These same clock lines are used to implement the transport mechanism as well. The amount of charge collected
at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength until
the potential well capacity is exceeded. At this point charge will 'bloom' into vertically adjacent pixels.
CHARGE TRANSPORT
Integrated charge is transported to the output in a two-step process. Rows of charge are first shifted line by line into
the horizontal CCD. 'Lines' of charge are then shifted to the output pixel by pixel. Referring to the timing diagram,
integration of charge is performed with φV1 and φV2 held low. Transfer to horizontal CCD begins when φV1 is
brought high causing charge from the φV1 and φV2 gates to combine under the φV1 gate.
φV1 and φV2 now reverse their polarity causing the charge packets to 'spill' forward under the φV2 gate of the next
pixel. The rising edge of φV2 also transfers the first line of charge into the horizontal CCD. A second phase transition
places the charge packets under the φV1 electrode of the next pixel. The sequence completes when φV1 is brought
low. Clocking of the vertical register in this way is known as accumulation mode clocking. Next, the horizontal CCD
reads out the first line of charge using traditional complementary clocking (using φH1 and φH2 pins) as shown. The
falling edge of φH2 forces a charge packet over the output gate (OG) onto one of the output nodes (floating diffusion)
which controls the output amplifier. The cycle repeats until all lines are read.
www.truesenseimaging.com
Revision 1.1 PS-0033 Pg 7

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