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KAF-40000 데이터시트 PDF




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부품번호 KAF-40000 기능
기능 CCD IMAGE SENSOR
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KAF-40000 데이터시트, 핀배열, 회로
KAF-40000
7304 (H) x 5478 (V) Full
Frame CCD Image Sensor
Description
The KAF−40000 Image Sensor is a high performance,
40-megapixel CCD. Based on the TRUESENSE 6.0 micron Full
Frame CCD Platform, the sensor features ultra-high resolution, broad
dynamic range, and a four-output architecture. A lateral overflow
drain suppresses image blooming, while an integrated Pulse Flush
Gate clears residual charge on the sensor with a single electrical pulse.
A Fast Dump Gate can be used to selectively remove a line of charge
to facilitate partial image readout. The sensor also utilizes the
TRUESENSE Transparent Gate Electrode to improve sensitivity
compared to the use of a standard front side illuminated polysilicon
electrode.
The sensor shares a common pin-out and electrical configuration
with the KAF−50100 Image Sensor, allowing a single camera design
to support both members of this sensor family.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Full Frame CCD (Square Pixels)
Total Number of Pixels
7410 (H) × 5566 (V) = 41.2 Mp
Number of Effective Pixels
7336 (H) × 5510 (V) = 40.4 Mp
Number of Active Pixels
7304 (H) × 5478 (V) = 40.0 Mp
Pixel Size
Active Image Size
6.0 mm (H) × 6.0 mm (V)
45.76 mm (H) × 35.34 mm (V)
54.78 mm (Diagonal),
645 1.3x Optical Format
Aspect Ratio
4:3
Horizontal Outputs
Saturation Signal
Output Sensitivity
4
42 ke
31 mV/e
Quantum Efficiency (Peak R, G, B)
Read Noise (f = 18 MHz)
Dark Signal (T = 60°C)
42%, 44%, 38%
13 e
42 pA/cm2
Dark Current Doubling Temperature 5.5°C
Dynamic Range (f = 18 MHz)
70.2 dB
Estimated Linear Dynamic Range
(f = 18 MHz)
69.3 dB
Charge Transfer Efficiency
Horizontal
Vertical
0.999995
0.999999
Blooming Protection
(4 ms Exposure Time)
1400X Saturation Exposure
Maximum Date Rate
18 MHz
Package
Ceramic PGA
Cover Glass
MAR Coated, 2 Sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 3
1
www.onsemi.com
Figure 1. KAF−40000 CCD Image Sensor
Features
TRUESENSE Transparent Gate Electrode
for High Sensitivity
Ultra-High Resolution
Board Dynamic Range
Low Noise Architecture
Large Active Imaging Area
Application
Digitization
Mapping/Aerial
Photography
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Publication Order Number:
KAF−40000/D




KAF-40000 pdf, 반도체, 판매, 대치품
KAF−40000
Charge Transport
The integrated charge from each pixel in the Vertical CCD
(VCCD) is transported to the output using a two-step
process. Each remaining line (row) of charge is first
transported from the VCCD to a dual parallel split horizontal
register (HCCD) using the V1 and V2 register clocks. The
transfer to the HCCD occurs on the falling edge of V2 while
H1A is held high. This line of charge may be readout
immediately (dual split) or may be passed through a transfer
gate (XG) into a second (B) HCCD register while the next
line loads into the first (A) HCCD register (dual parallel
split). Readout of each line in the HCCD is always split at the
middle and, thus, either two or four outputs are used. Left (or
right) outputs carry image content from pixels in the left (or
right) columns of the VCCD. A separate connection to the
last H1 phase (H1L) is provided to improve the transfer
speed of charge to the output amplifier. On each falling edge
of H1L, a new charge packet is sensed by the output
amplifier. Left and right HCCDs are electrically isolated
from each other except for the common transfer gate (XG).
Pulsed Flush Gate/Fast Dump Gate
The Pulsed Flush Gate (PFG) feature is used to drain the
charge of all pixels prior to exposure. The exception is pixels
in the Fast Dump Gate (FDG) row that are drained using the
separate FDG pin. Draining is accomplished by first
clocking V2 high while V1 is held low. This forces all charge
into the V2 phase of the pixel. While V2 is high, PFG (or
FDG) may be clocked high to begin draining the signal from
the pixel to the LOD. Charge transfer out of the pixel is fully
completed only after V2 has been clocked low plus some
characteristic time.
Horizontal Register
Output Structure
The output consists of a floating diffusion connected to
a three-stage source follower. Charge presented to the
floating diffusion (FD) is converted into a voltage and is
current amplified in order to drive off-chip loads. The
resulting voltage change seen at the output is linearly related
to the amount of charge placed on the FD. Once the signal
has been sampled by the system electronics, the reset gate
(RG) is clocked to remove the signal and FD is reset to the
potential applied by reset drain (RD). Increased signal at the
floating diffusion reduces the voltage seen at the output pin.
To activate the output structure, an off-chip current source
must be added to the VOUT pin of the device. See Figure 4.
H2
H1
H2
HIL
OG
RG
RD
VSUB
HCCD
Charge
Transfer
VDD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 3. Output Architecture (Each Output)
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KAF-40000 전자부품, 판매, 대치품
KAF−40000
Table 3. PIN DESCRIPTION
Pin Name
Description
A1
VSUB
Substrate
A2 VDDLA Output Amplifier Supply, Left A
A3
VSSL
Output Amplifier Return, Left
A4
RDL
Reset Drain, Left
A5 VDDLB Output Amplifier Supply, Left B
A6
H1AL
Horizontal Phase 1, A Left
A7 H2L Horizontal Phase 2, Left
A10 H2R Horizontal Phase 2, Right
A11 H1AR Horizontal Phase 1, A Right
A12 VDDRB Output Amplifier Supply, Right B
A13 RDR Reset Drain, Right
A14 VSSR Output Amplifier Return, Right
A15 VDDRA Output Amplified Supply, Right A
A16 VSUB Substrate
B1 VOUTLA Video Output, Left A
B2 VOUTLB Video Output, Left B
B3
OGL
Output Gate, Left
B4
RGL
Reset Gate, Left
B5
H1LL
Horizontal Phase 1, Last Gate, Left
B6
H1BL
Horizontal Phase 1, B Left
B7 XG Horizontal Transfer Gate
B8
VSUB
Substrate
B9
VSUB
Substrate
B10 NC No Connection
B11 H1BR Horizontal Phase 1, B Right
B12 H1LR Horizontal Phase 1, Last Gate, Right
B13 RGR Reset Gate, Right
B14 OGR Output Gate, Right
B15 VOUTRB Video Output, Right B
B16 VOUTRA Video Output, Right A
Pin Name
Description
C1
LOD
Lateral Overflow Drain
C2
PFG
Pulse Flush Gate
C3 V1 Vertical Phase 1
C4 V2 Vertical Phase 2
C5
PFG
Pulse Flush Gate
C6
VSUB
Substrate
C7
VSUB
Substrate
C8
PFG
Pulse Flush Gate
C9 V2 Vertical Phase 2
C10 V1 Vertical Phase 1
C11 PFG Pulse Flush Gate
C12 LOD Lateral Overflow Drain
D1
VSUB
Substrate
D2
FDG
Fast Dump Gate
D3 V1 Vertical Phase 1
D4 V2 Vertical Phase 2
D5
LOD
Lateral Overflow Drain
D8
LOD
Lateral Overflow Drain
D9 V2 Vertical Phase 2
D10 V1 Vertical Phase 1
D11 FDG Fast Dump Gate
D12 VSUB Substrate
NOTE: The leads are on a 0.100spacing.
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