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기능 CCD IMAGE SENSOR
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KAF-4320-AAA 데이터시트, 핀배열, 회로
KAF-4320
2084 (H) x 2085 (V) Full
Frame CCD Image Sensor
Description
The KAF−4320 Image Sensor is a high performance monochrome
area CCD (charge-coupled device) image sensor designed for a wide
range of image sensing applications.
The sensor incorporates true two-phase CCD technology,
simplifying the support circuits required to drive the sensor as well as
reducing dark current without compromising charge capacity.
The sensor also utilizes the TRUESENSE Transparent Gate Electrode
to improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
The full imaging array is read out of four outputs, each of which is
driven by a low impedance two stage source follower that provides
a high conversion gain. This combination enables low noise at a net
readout rate of 12 MHz (3 MHz per output).
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Full Frame CCD
Total Number of Pixels
2092 (H) × 2093 (V)
Number of Active Pixels
2084 (H) × 2085 (V) = approx. 4.3 Mp
Pixel Size
24 mm (H) × 24 mm (V)
Active Image Size
50.02 mm (H) × 50.02 mm (V)
70.7 mm (Diagonal)
645 Optical Format
Die Size
Output Sensitivity
52.3 mm (H) × 52.7 mm (V)
10 mV/e
Saturation Signal
500,000 electrons
Readout Noise
20 electrons (3 MHz)
Outputs
Dark Current
4
< 15 pA/cm2
Dark Current Doubling
Temperature
6.4°C
Dynamic Range
20,000 : 1
Blooming Suppression
None
Maximum Date Rate
3 MHz
Package
PGA Package
Cover Glass
Clear
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
www.onsemi.com
Figure 1. KAF−4320 Full Frame CCD
Image Sensor
Features
True Two Phase Full Frame Architecture
TRUESENSE Transparent Gate Electrode
for High Sensitivity
Applications
Medical Imaging
Scientific Imaging
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
KAF−4320/D




KAF-4320-AAA pdf, 반도체, 판매, 대치품
KAF−4320
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the sensor. These photon induced
electrons are collected locally by the formation of potential
wells at each photogate or pixel site. The number of
electrons collected is linearly dependent on light level and
exposure time and non-linearly dependent on wavelength.
When the pixel’s capacity is reached, excess electrons will
leak into the adjacent pixels within the same column. This
is termed blooming. During the integration period, the fV1
and fV2 register clocks are held at a constant (low) level.
See Figure 17.
Charge Transport
Referring again to Figure 17, the integrated charge from
each photogate is transported to the output using a two-step
process. Each line (row) of charge is first transported from
the vertical CCD to the horizontal CCD register using the
fV1 and fV2 register clocks. The horizontal CCD is
presented a new line on the falling edge of fV2 while fH1
is held high. The horizontal CCD then transports each line,
pixel by pixel, to the output structure by alternately clocking
the fH1 and fH2 pins in a complementary fashion. On each
falling edge of fH1L a new charge packet is transferred onto
a floating diffusion and sensed by the output amplifier.
Output Structure
Charge presented to the floating diffusion is converted
into a voltage and current amplified in order to drive off-chip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the
floating diffusion. Once the signal has been sampled by the
system electronics, the reset gate (fR) is clocked to remove
the signal and the floating diffusion is reset to the potential
applied by VRD. (See Figure 4). More signal at the floating
diffusion reduces the voltage seen at the output pin. In order
to activate the output structure, an off-chip load must be
added to the VOUT pin of the device such as shown in
Figure 6.
If charge binning is desired, the charge can be combined
at the output node or it can be combined in the fH1L gate
and then presented to the output node.
Dark Reference Pixels
There are 4 light shielded pixels at the beginning of each
line. There are 4 dark lines at the start of every frame and 4
dark lines at the end of each frame. Since there are outputs
at each of the four corners, the light shield will affect the
beginning of each line from each output, and for the first four
lines from each of the outputs. Under normal circumstances,
these pixels do not respond to light. However, dark reference
pixels in close proximity to an active pixel can scavenge
signal depending on light intensity and wavelength and
therefore will not represent the true dark signal.
Dummy Pixels
Within the horizontal shift register are 4−1/2 leading
pixels that are not associated with a column of pixels within
the vertical register. These pixels contain only horizontal
shift register dark current signal and do not respond to light.
A few leading dummy pixels may scavenge false signal
depending on operating conditions.
H2
H1
H2
H1
VOG
R
VRD
VLG
HCCD
Charge
Transfer
Floating
Diffusion
VDD
VOUT
Source
Follower
#1
Figure 4. Output Architecture
Source
Follower
#2
www.onsemi.com
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KAF-4320-AAA 전자부품, 판매, 대치품
KAF−4320
IMAGING PERFORMANCE
Electro-Optical Specifications
All values measured at 25°C, and nominal operating conditions. These parameters exclude defective pixels.
Table 5. SPECIFICATIONS
Description
Saturation Signal
Vertical CCD Capacity
Horizontal CCD Capacity
Output Node Capacity
Symbol
NSAT
Min.
500,000
Nom.
650,000
850,000
550,000
Max.
Units
e/pix
Notes
1
Verification
Plan
Design10
Quantum Efficiency (see Figure 6)
Photoresponse Non-Linearity
Photoresponse Non-Uniformity
PRNL
PRNU
< 1.0
0.8
2.0
2.0
Design10
% 2 Design10
% 3 Design10
Channel to Channel Gain Difference
Dark Signal
Dark Signal Doubling Temperature
Dark Signal Non-Uniformity
Dynamic Range
G
JDARK
DSNU
DR
86
0.2
2,507
6.3
300
87.5
5
54,015
7
540
%
e/pix/sec
°C
e/pix/sec
dB
8
4
5
6
Die9
Die9
Design10
Die9
Design10
Output Amplifier DC Offset
VODC
VRD − 4
VRD − 3
VRD − 2
V
Die9
Output Amplifier Sensitivity
VOUT/Ne−
9
10 11 mV/e
Design10
Output Amplifier Output Impedance
ZOUT
150
W
Die9
Noise Floor
ne−
17
24
electrons
7
Design10
1. The maximum output video amplitude limits the charge capacity and dynamic range. The maximum charge capacity is determined from
a photon transfer measurement and is defined as the point where the mean-variance fails to demonstrate the theoretical behavior.
2. Worst case deviation from straight line fit, between 0.1% and 95% of VSAT.
3. One Sigma deviation of a 1042 × 1042 sample (data from one output) when the CCD is illuminated uniformly at half of saturation, excluding
defective pixels. [100 (Std Deviation / Average)]
4. Average of all pixels with no illumination at 25°C.
5. Average dark signal of any of 16 × 16 blocks within the sensor (each block is 130 × 130 pixels).
6. The dynamic range limited by the noise of the output amplifier (i.e. at temperatures less than –10°C), pixel frequency = 3 MHz, and
bandwidth = 10 MHz.
7. Noise floor of the CCD amplifier assuming correlated double sampling, pixel frequency = 3 MHz, and bandwidth = 10 MHz.
8. DG = abs (100 (1 – [response of a channel] / [average response of all four channels])). The specified gain difference is the combination
of all the gain errors on the CCD sensor and the analog signal processing in the test system.
9. A parameter that is measured on every sensor during production testing.
10. A parameter that is quantified during the design verification activity.
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KAF-4320-AAA

CCD IMAGE SENSOR

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