Datasheet.kr   

KAF-50100-ABA 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 KAF-50100-ABA은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 KAF-50100-ABA 자료 제공

부품번호 KAF-50100-ABA 기능
기능 CCD IMAGE SENSOR
제조업체 ON Semiconductor
로고 ON Semiconductor 로고


KAF-50100-ABA 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 25 페이지수

미리보기를 사용할 수 없습니다

KAF-50100-ABA 데이터시트, 핀배열, 회로
KAF-50100
8176 (H) x 6132 (V) Full
Frame CCD Image Sensor
Description
The KAF−50100 Image Sensor is a high performance,
50-megapixel CCD. Based on the TRUESENSE 6.0 micron Full
Frame CCD Platform, the sensor features ultra-high resolution, broad
dynamic range, and a four-output architecture. A lateral overflow
drain suppresses image blooming, while an integrated Pulse Flush
Gate clears residual charge on the sensor with a single electrical pulse.
A Fast Dump Gate can be used to selectively remove a line of charge
to facilitate partial image readout. The sensor also utilizes the
TRUESENSE Transparent Gate Electrode to improve sensitivity
compared to the use of a standard front side illuminated polysilicon
electrode.
The sensor shares a common pin-out and electrical configuration
with the KAF−40000 Image Sensor, allowing a single camera design
to support both members of this sensor family.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Full Frame CCD (Square Pixels)
8304 (H) × 6220 (V) = 51.6 Mp
8208 (H) × 6164 (V) = 50.5 Mp
8176 (H) × 6132 (V) = 50.1 Mp
6.0 mm (H) × 6.0 mm (V)
49.1 mm (H) × 36.8 mm (V)
61.3 mm (Diagonal),
645 1.1x Optical Format
Aspect Ratio
4:3
Horizontal Outputs
Saturation Signal
Output Sensitivity
Quantum Efficiency
KAF−50100−CAA
KAF−50100−AAA
KAF−50100−ABA (with Lens)
Read Noise (f = 18 MHz)
Dark Signal (T = 60°C)
Dark Current Doubling Temperature
Dynamic Range (f = 18 MHz)
4
40.3 ke
31 mV/e
22%, 22%, 16% (Peak R, G, B)
25%
62%
12.5 e
42 pA/cm2
5.7°C
70.2 dB
Estimated Linear Dynamic Range
(f = 18 MHz)
69.3 dB
Charge Transfer Efficiency
Horizontal
Vertical
0.999995
0.999999
Blooming Protection
(4 ms Exposure Time)
800X Saturation Exposure
Maximum Date Rate
18 MHz
Package
Ceramic PGA
Cover Glass
MAR Coated, 2 Sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 3
1
www.onsemi.com
Figure 1. KAF−50100 Full Frame CCD
Image Sensor
Features
TRUESENSE Transparent Gate Electrode
for High Sensitivity
Ultra-High Resolution
Board Dynamic Range
Low Noise Architecture
Large Active Imaging Area
Applications
Digitization
Mapping/Aerial
Photography
Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Publication Order Number:
KAF−50100/D




KAF-50100-ABA pdf, 반도체, 판매, 대치품
KAF−50100
Charge Transport
The integrated charge from each pixel in the Vertical CCD
(VCCD) is transported to the output using a two-step
process. Each remaining line (row) of charge is first
transported from the VCCD to a dual parallel split horizontal
register (HCCD) using the V1 and V2 register clocks.
The transfer to the HCCD occurs on the falling edge of V2
while H1A is held high. This line of charge may be readout
immediately (dual split) or may be passed through a transfer
gate (XG) into a second (B) HCCD register while the next
line loads into the first (A) HCCD register (dual parallel
split). Readout of each line in the HCCD is always split at the
middle and, thus, either two or four outputs are used. Left
(or right) outputs carry image content from pixels in the left
(or right) columns of the VCCD. A separate connection to
the last H1 phase (H1L) is provided to improve the transfer
speed of charge to the output amplifier. On each falling edge
of H1L, a new charge packet is sensed by the output
amplifier. Left and right HCCDs are electrically isolated
from each other except for the common transfer gate (XG).
Pulsed Flush Gate/Fast Dump Gate
The Pulsed Flush Gate (PFG) feature is used to drain the
charge of all pixels prior to exposure. The exception is pixels
in the Fast Dump Gate (FDG) row that are drained using the
separate FDG pin. Draining is accomplished by first
clocking V2 high while V1 is held low. This forces all charge
into the V2 phase of the pixel. While V2 is high, PFG
(or FDG) may be clocked high to begin draining the signal
from the pixel to the LOD. Charge transfer out of the pixel
is fully completed only after V2 has been clocked low plus
some characteristic time.
Horizontal Register
Output Structure
The output consists of a floating diffusion connected to
a three-stage source follower. Charge presented to the
floating diffusion (FD) is converted into a voltage and is
current amplified in order to drive off-chip loads.
The resulting voltage change seen at the output is linearly
related to the amount of charge placed on the FD. Once the
signal has been sampled by the system electronics, the reset
gate (RG) is clocked to remove the signal and FD is reset to
the potential applied by reset drain (RD). Increased signal at
the floating diffusion reduces the voltage seen at the output
pin. To activate the output structure, an off-chip current
source must be added to the VOUT pin of the device. See
Figure 4.
H2
H1
H2
HIL
OG
RG
RD
VSUB
HCCD
Charge
Transfer
VDD
Floating
Diffusion
VOUT
VSS
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
Figure 3. Output Architecture (Each Output)
www.onsemi.com
4

4페이지










KAF-50100-ABA 전자부품, 판매, 대치품
KAF−50100
Table 3. PIN DESCRIPTION
Pin Name
Description
A1
VSUB
Substrate
A2 VDDLA Output Amplifier Supply, Left A
A3
VSSL
Output Amplifier Return, Left
A4 RDL Reset Drain, Left
A5 VDDLB Output Amplifier Supply, Left B
A6
H1AL
Horizontal Phase 1, A Left
A7 H2L Horizontal Phase 2, Left
A12 H2R Horizontal Phase 2, Right
A13 H1AR Horizontal Phase 1, A Right
A14 VDDRB Output Amplifier Supply, Right B
A12 RDR Reset Drain, Right
A16 VSSR Output Amplifier Return, Right
A17 VDDRA Output Amplified Supply, Right A
A18 VSUB Substrate
B1 VOUTLA Video Output, Left A
B2 VOUTLB Video Output, Left B
B3
OGL
Output Gate, Left
B4
RGL
Reset Gate, Left
B5
H1LL
Horizontal Phase 1, Last Gate, Left
B6
H1BL
Horizontal Phase 1, B Left
B7 XG Horizontal Transfer Gate
B8
VSUB
Substrate
B11 VSUB Substrate
B12 NC No Connection
B13 H1BR Horizontal Phase 1, B Right
B14 H1LR Horizontal Phase 1, Last Gate, Right
B15 RGR Reset Gate, Right
B16 OGR Output Gate, Right
B17 VOUTRB Video Output, Right B
B18 VOUTRA Video Output, Right A
Pin Name
Description
C1
LOD
Lateral Overflow Drain
C2
PFG
Pulse Flush Gate
C3 V1 Vertical Phase 1
C4 V2 Vertical Phase 2
C5
PFG
Pulse Flush Gate
C6
VSUB
Substrate
C13 VSUB Substrate
C14 PFG Pulse Flush Gate
C15 V2 Vertical Phase 2
C16 V1 Vertical Phase 1
C17 PFG Pulse Flush Gate
C18 LOD Lateral Overflow Drain
D1
VSUB
Substrate
D2
FDG
Fast Dump Gate
D3 V1 Vertical Phase 1
D4 V2 Vertical Phase 2
D5
LOD
Lateral Overflow Drain
D14 LOD Lateral Overflow Drain
D15 V2 Vertical Phase 2
D16 V1 Vertical Phase 1
D17 FDG Fast Dump Gate
D18 VSUB Substrate
NOTE: The leads are on a 0.100spacing.
www.onsemi.com
7

7페이지


구       성 총 25 페이지수
다운로드[ KAF-50100-ABA.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
KAF-50100-ABA

CCD IMAGE SENSOR

ON Semiconductor
ON Semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵