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KAI-02150-FBA 데이터시트 PDF




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부품번호 KAI-02150-FBA 기능
기능 CCD IMAGE SENSOR
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KAI-02150-FBA 데이터시트, 핀배열, 회로
KAI-02150
1920 (H) x 1080 (V) Interline
CCD Image Sensor
Description
The KAI−02150 Image Sensor is a 1080p (1920 × 1080) CCD in
a 2/3optical format. Based on the TRUESENSE 5.5-micron Interline
Transfer CCD Platform, the sensor features broad dynamic range,
excellent imaging performance, and a flexible readout architecture
that enables use of 1, 2, or 4 outputs for full resolution readout up to
64 frames per second. A vertical overflow drain structure suppresses
image blooming and enables electronic shuttering for precise exposure
control.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Typical Value
Interline CCD, Progressive Scan
2004 (H) × 1144 (V)
1960 (H) × 1120 (V)
1920 (H) × 1080 (V)
5.5 mm (H) × 5.5 mm (V)
10.56 mm (H) × 5.94 mm (V)
12.1 mm (Diagonal),
2/3Optical Format
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Quantum Efficiency
Pan (−ABA, −PBA)
R, G, B (−FBA, −QBA)
R, G, B (−CBA, −PBA)
16:9
1, 2, or 4
20,000 electrons
34 mV/e
44%
31%, 37%, 38%
29%, 37%, 39%
Base ISO
KAI−02150−ABA
KAI−02150−FBA
KAI−02150−CBA
KAI−02150−PBA
Read Noise (f = 40 MHz)
Dark Current
Photodiode/VCCD
330
170
150
330
12 erms
7/100 e/s
Dark Current Doubling Temp
Photodiode/VCCD
7°C/9°C
Dynamic Range
Charge Transfer Efficiency
Blooming Suppression
Smear
Image Lag
Maximum Pixel Clock Speed
Maximum Frame Rate
Quad/Dual/Single Output
64 dB
0.999999
> 300 X
−100 dB
< 10 electrons
40 MHz
64/33/17 fps
Package
68 Pin PGA
64 Pin CLCC
Cover Glass
AR Coated, 2-Sides or Clear Glass
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 6
1
www.onsemi.com
Figure 1. KAI−02150 Interline CCD
Image Sensor
Features
Bayer Color Pattern, TRUESENSE Sparse
Color Filter Pattern, and Monochrome
Configurations
Progressive Scan Readout
Flexible Readout Architecture
High Frame Rate
High Sensitivity
Low Noise Architecture
Excellent Smear Performance
Package Pin Reserved for Device
Identification
Applications
Industrial Imaging
Medical Imaging
Security
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Publication Order Number:
KAI−02150/D




KAI-02150-FBA pdf, 반도체, 판매, 대치품
DEVICE DESCRIPTION
Architecture
KAI−02150
RDc RDd
Rc Rd
VDDc
VOUTc
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉGND
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉOGc
1 10 22 20
960 960
1 Dummy
12
20 22 10 1
VDDd
VOUTd
GND
OGd
H2SLc 20 H2SLd
V1T V1T
V2T V2T
V3T V3T
V4T V4T
ESD 22 20
1920 (H) × 1080 (V)
5.5 mm × 5.5 mm Pixels
20 22
DevID
ESD
V1B V1B
V2B V2B
V3B V3B
V4B V4B
RDa
Ra
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉVDDa
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉVOUTa
1 10 22 20
20 Buffer
12 Dark
1 Dummy
(Last VCCD Phase = V1 H1S)
960 960
20 22 10 1
RDb
Rb
VDDb
VOUTb
GND
OGa
H2SLa
GND
OGb
H2SLb
Figure 2. Block Diagram
Dark Reference Pixels
There are 12 dark reference rows at the top and 12 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
Active Buffer Pixels
20 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and non-uniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
ESD Protection
Adherence to the power-up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor. See
Power-Up and Power-Down Sequence section.
www.onsemi.com
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KAI-02150-FBA 전자부품, 판매, 대치품
KAI−02150
Table 4. PGA PACKAGE PIN DESCRIPTION (continued)
Pin Name
Description
25 Rb Reset Gate, Quadrant b
26
RDb
Reset Drain, Quadrant b
27
GND
Ground
28
VOUTb
Video Output, Quadrant b
29
VDDb
Output Amplifier Supply, Quadrant b
30 V2B Vertical CCD Clock, Phase 2, Bottom
31 V1B Vertical CCD Clock, Phase 1, Bottom
32 V4B Vertical CCD Clock, Phase 4, Bottom
33 V3B Vertical CCD Clock, Phase 3, Bottom
34
ESD
ESD Protection Disable
35 V3T Vertical CCD Clock, Phase 3, Top
36
DevID
Device Identification
37 V1T Vertical CCD Clock, Phase 1, Top
38 V4T Vertical CCD Clock, Phase 4, Top
39
VDDd
Output Amplifier Supply, Quadrant d
40 V2T Vertical CCD Clock, Phase 2, Top
41
GND
Ground
42
VOUTd
Video Output, Quadrant d
43 Rd Reset Gate, Quadrant d
44
RDd
Reset Drain, Quadrant d
45
H2SLd
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d
46
OGd
Output Gate, Quadrant d
47
H1Bd
Horizontal CCD Clock, Phase 1, Barrier, Quadrant d
48
H2Bd
Horizontal CCD Clock, Phase 2, Barrier, Quadrant d
49
H2Sd
Horizontal CCD Clock, Phase 2, Storage, Quadrant d
50
H1Sd
Horizontal CCD Clock, Phase 1, Storage, Quadrant d
51 N/C No Connect
52
SUB
Substrate
53
H2Sc
Horizontal CCD Clock, Phase 2, Storage, Quadrant c
54
H1Sc
Horizontal CCD Clock, Phase 1, Storage, Quadrant c
55
H1Bc
Horizontal CCD Clock, Phase 1, Barrier, Quadrant c
56
H2Bc
Horizontal CCD Clock, Phase 2, Barrier, Quadrant c
57
H2SLc
Horizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c
58
OGc
Output Gate, Quadrant c
59 Rc Reset Gate, Quadrant c
60 RDc Reset Drain, Quadrant c
61
GND
Ground
62
VOUTc
Video Output, Quadrant c
63
VDDc
Output Amplifier Supply, Quadrant c
64 V2T Vertical CCD Clock, Phase 2, Top
65 V1T Vertical CCD Clock, Phase 1, Top
66 V4T Vertical CCD Clock, Phase 4, Top
67 V3T Vertical CCD Clock, Phase 3, Top
68
ESD
EDS Protection Disable
1. Liked named pins are internally connected and should have a common drive signal.
2. N/C pins (17, 51) should be left floating.
www.onsemi.com
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