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KAI-04022-AAA 데이터시트 PDF




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부품번호 KAI-04022-AAA 기능
기능 CCD IMAGE SENSOR
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KAI-04022-AAA 데이터시트, 핀배열, 회로
KAI-04022
2048 (H) x 2048 (V) Interline
CCD Image Sensor
Description
The KAI−04022 Image Sensor is a high-performance 4-million
pixel sensor designed for a wide range of medical, scientific and
machine vision applications. The 7.4 mm square pixels with
microlenses provide high sensitivity and the large full well capacity
results in high dynamic range. The two high-speed outputs and
binning capabilities allow for 16−50 frames per second (fps) video rate
for the progressively scanned images. The vertical overflow drain
structure provides anti-blooming protection and enables electronic
shuttering for precise exposure control. Other features include low
dark current, negligible lag and low smear.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Interline CCD, Progressive Scan
2112 (H) × 2072 (V)
2056 (H) × 2062 (V)
2048 (H) × 2048 (V)
7.4 mm (H) × 7.4 mm (V)
15.15 mm (H) × 15.15 mm (V),
21.43 mm (Diagonal),
4/3Optical Format
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Peak Quantum Efficiency
KAI−04022−ABA
KAI−04022−FBA (BRG)
KAI−04022−CBA (BRG)
Read Noise (f = 10 MHz)
Dark Current
Dark Current Doubling Temp.
Dynamic Range
1:1
1 or 2
40,000 e
33 mV/e
50%
44%, 42%, 36%
45%, 42%, 35%
9 e, rms
< 0.5 nA/cm2
7°C
72 dB
Charge Transfer Efficiency
> 0.999999
Blooming Suppression
300X
Smear
Image Lag
−80 dB
< 10 e
Maximum Frame Rates
8 fps (Single Output)
16 fps (Single Output)
Package
34-pin, CERDIP
Cover Glass
AR Coated, 2-Side
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
www.onsemi.com
Figure 1. KAI−04022 Interline CCD
Image Sensor
Features
High Resolution
High Sensitivity
High Dynamic Range
Low Noise Architecture
High Frame Rate
Binning Capability for Higher Frame Rate
Electronic Shutter
Applications
Intelligent Transportation Systems
Machine Vision
Scientific Imaging
Surveillance
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 2
1
Publication Order Number:
KAI−04022/D




KAI-04022-AAA pdf, 반도체, 판매, 대치품
KAI−04022
Pixel
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7.4 mm
True Two Phase Burried Channel VCCD
Lightshield over VCCD not shown
Cross Section Down Through VCCD
V1 V2
V1
ÉÉnÉÉÉÉn−ÉÉn ÉÉn−ÉÉ
p Well (GND)
Direction of
Charge
Transfer
n Substrate
Cross Section Through
Photodiode and VCCD Phase 1
Cross Section Through Photodiode
and VCCD Phase 2 at Transfer Gate
Photodiode
Light Shield
Transfer
ÉÉp
p+
n
ÉÉÉÉÏÏp ÏÏÏÏÏÏVnp1 ÏÏÏÏÏÏÉÉp
ÉÉÉÉ Gate
p p+
n
Light Shield
ÏÏÏÏVÏÏ2pnÏÏÏÏÏÏÉÉpÉÉ
pp
n Substrate
n Substrate
NOTE: Drawings not scale.
Cross Section Showing Lenslet
Lenslet
Red Color Filter
Light Shield
VCCD
Photodiode
Light Shield
VCCD
Figure 3. Pixel Architecture
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
www.onsemi.com
4

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KAI-04022-AAA 전자부품, 판매, 대치품
KAI−04022
Horizontal Register Split
H1 H2 H2 H1
H1 H2
H2 H1 H1 H2
H1BL
H2SL
H2BL
H1SL
H1BL
H2SL
H1BR
H1SR
H2BR
H2SR
Pixel
1068
Single Output
H1 H2 H2 H1 H1 H2
Pixel
1069
H1 H1 H2 H2
H1BL
H2SL
H2BL
H1SL
H1BL H2SL
H1BR H1SR
H2BR H2SR
Pixel
1068
Dual Output
Figure 6. Horizontal Register
Pixel
1068
Single Output Operation
When operating the sensor in single output mode all pixels
of the image sensor will be shifted out the Video L output
(pin 12). To conserve power and lower heat generation the
output amplifier for Video R may be turned off by
connecting VDDR (pin 24) and VOUTR (pin 23) to GND
(0 V).
The H1 timing from the timing diagrams should be
applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing
should be applied to H2SL, H2BL, H2SR, and H1BR. In
other words, the clock driver generating the H1 timing
should be connected to pins 16, 15, 19, and 21. The clock
driver generating the H2 timing should be connected to pins
17, 14, 18, and 20. The horizontal CCD should be clocked
for 12 empty pixels plus 28 light shielded pixels plus 2,056
photoactive pixels plus 28 light shielded pixels for a total of
2,124 pixels.
Dual Output Operation
In dual output mode the connections to the H1BR and
H2BR pins are swapped from the single output mode to
change the direction of charge transfer of the right side
horizontal shift register. In dual output mode both VDDL
and VDDR (pins 11, 24) should be connected to 15 V.
The H1 timing from the timing diagrams should be applied
to H1SL, H1BL, H1SR, H1BR, and the H2 timing should be
applied to H2SL, H2BL, H2SR, and H2BR. The clock driver
generating the H1 timing should be connected to pins 16, 15,
19, and 20. The clock driver generating the H2 timing should
be connected to pins 17, 14, 18, and 21. The horizontal CCD
should be clocked for 12 empty pixels plus 28 light shielded
pixels plus 1,028 photoactive pixels for a total of 1,068
pixels. If the camera is to have the option of dual or single
output mode, the clock driver signals sent to H1BR and
H2BR may be swapped by using a relay. Another alternative
is to have two extra clock drivers for H1BR and H2BR and
invert the signals in the timing logic generator. If two extra
clock drivers are used, care must be taken to ensure the rising
and falling edges of the H1BR and H2BR clocks occur at the
same time (within 3 ns) as the other HCCD clocks.
www.onsemi.com
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KAI-04022-AAA

CCD IMAGE SENSOR

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