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PDF KAI-2001 Data sheet ( Hoja de datos )
| Número de pieza | KAI-2001 | |
| Descripción | CCD IMAGE SENSOR | |
| Fabricantes | ON Semiconductor | |
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KAI-2001
1600 (H) x 1200 (V) Interline
CCD Image Sensor
Description
The KAI−2001 Image Sensor is a high-performance 2-million pixel
sensor designed for a wide range of medical, scientific and machine
vision applications. The 7.4 mm square pixels with microlenses
provide high sensitivity and the large full well capacity results in high
dynamic range. The split horizontal register offers a choice of single or
dual output allowing either 15 or 30 frame per second (fps) video rate
for the progressively scanned images. Also included is a fast line
dump for sub-sampling at higher frame rates. The vertical overflow
drain structure provides anti-blooming protection and enables
electronic shuttering for precise exposure control. Other features
include low dark current, negligible lag and low smear.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Pixel Size
Active Image Size
Typical Value
Interline CCD, Progressive Scan
1640 (H) × 1214 (V)
1608 (H) × 1208 (V)
1600 (H) × 1200 (V)
7.4 mm (H) × 7.4 mm (V)
13.38 mm (H) × 9.52 mm (V),
14.803 mm (Diagonal),
1″ Optical Format
Aspect Ratio
4:3
Number of Outputs
Saturation Signal
1 or 2
40,000 e−
Quantum Efficiency
−ABA
−CBA (RGB)
55%
45%, 42%, 35%
Output Sensitivity
16 mV/e−
Total System Noise
40 MHz
20 MHz
40 e−
23 e−
Dark Current
< 0.5 nA/cm2
Dark Current Doubling Temp.
7°C
Dynamic Range
60 dB
Charge Transfer Efficiency
> 0.999999
Blooming Suppression
300X
Smear
Image Lag
80 dB
< 10 e−
Maximum Data Rate
40 MHz
Package
32-pin, CERDIP
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
www.onsemi.com
Figure 1. KAI−2001 Interline CCD
Image Sensor
Features
• High Resolution
• High Sensitivity
• High Dynamic Range
• Low Noise Architecture
• High Frame Rate
• Binning Capability for Higher Frame Rate
• Electronic Shutter
Applications
• Machine Vision
• Scientific
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 2
1
Publication Order Number:
KAI−2001/D
1 page  
KAI−2001
Vertical to Horizontal Transfer
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Direction of
Horizontal
Charge Transfer
Figure 4. Vertical to Horizontal Transfer Architecture
When the V1 and V2 timing inputs are pulsed, charge in
every pixel of the VCCD is shifted one row towards the
HCCD. The last row next to the HCCD is shifted into the
HCCD. When the VCCD is shifted, the timing signals to the
HCCD must be stopped. H1 must be stopped in the high state
and H2 must be stopped in the low state. The HCCD
clocking may begin tHD ms after the falling edge of the V1
and V2 pulse.
Charge is transferred from the last vertical CCD phase into
the H1S horizontal CCD phase. Refer to Figure 27 for an
example of timing that accomplishes the vertical to
horizontal transfer of charge.
If the fast line dump is held at the high level (FDH) during
a vertical to horizontal transfer, then the entire line is
removed and not transferred into the horizontal register.
www.onsemi.com
5
5 Page 
KAI−2001
Table 6. PERFORMANCE SPECIFICATIONS (continued)
Description
Symbol
Min.
Nom.
Max.
Unit
ALL CONFIGURATIONS
Output Amplifier Bandwidth
Output Amplifier Impedance
Output Amplifier Sensitivity
f−3DB
−
140
− MHz
ROUT
100
130
200
W
DV/DN
−
16
− mV/e−
KAI−2001−ABA CONFIGURATION
Peak Quantum Efficiency
QEMAX
45
55 N/A %
Peak Quantum Efficiency Wavelength
lQE
N/A
500
N/A nm
KAI−2001−CBA CONFIGURATION
Peak Quantum Efficiency
Red
Green
Blue
QEMAX
−
−
−
%
35 N/A
42 N/A
45 N/A
Peak Quantum Efficiency Wavelength
Red
Green
Blue
lQE
−
−
−
nm
620 N/A
540 N/A
470 N/A
NOTE: N/A = Not Applicable.
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning.
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 20 MHz.
5. Includes system electronics noise, dark pattern noise and dark current shot noise at 40 MHz.
6. Uses 20LOG (PNe / ne−T).
Sampling
Plan
Design
Die
Design
Design
Design
Design
Design
Temperature
Tested at
(5C)
www.onsemi.com
11
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