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HY57V161610ET-6I 데이터시트 PDF




Hynix Semiconductor에서 제조한 전자 부품 HY57V161610ET-6I은 전자 산업 및 응용 분야에서
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부품번호 HY57V161610ET-6I 기능
기능 2 Banks x 512K x 16 Bit Synchronous DRAM
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HY57V161610ET-6I 데이터시트, 핀배열, 회로
HY57V161610ET-I
2 Banks x 512K x 16 Bit Synchronous DRAM
DESCRIPTION
THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic appli-
cations which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16.
HY57V161610E is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initi-
ated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A
burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a
new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
• Single 3.0V to 3.6V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin
pitch
• All inputs and outputs referenced to positive edge of system
clock
• Data mask function by UDQM/LDQM
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
• Programmable CAS Latency ; 1, 2, 3 Clocks
• Internal two banks operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY57V161610ET-5I
HY57V161610ET-55I
HY57V161610ET-6I
HY57V161610ET-7I
HY57V161610ET-8I
HY57V161610ET-10I
HY57V161610ET-15I
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
66MHz
Note :
1. VDD(min) of HY57V161610ET-5I/55I is 3.15V
Organization
Interface
2Banks x 512Kbits x 16
LVTTL
Package
400mil
50pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for
use of circuits described. No patent licenses are implied
Rev. 0.1 / Nov. 2003
1




HY57V161610ET-6I pdf, 반도체, 판매, 대치품
HY57V161610ET-I
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
Soldering Temperature·Time
Symbol
TA
TSTG
VIN, VOUT
VDD
IOS
PD
TSOLDER
Rating
-40 ~ 85
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260·10
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0°C to 70°C)
Parameter
Power Supply Voltage
Input high voltage
Input low voltage
Symbol
VDD, VDDQ
VIH
VIL
Min
3.0
2.0
-0.3
Note :
1.All voltages are referenced to VSS = 0V.
2.VDD(min) is 3.15V when HY57V161610ET-7I operates at CAS latency=2
3.VDD(min) of HY57V161610ET-5I/55I is 3.15V
4.Vih(Max) : 4.6V AC pulse width with < 3ns of duration.
5.Vil(min) : -1.5V AC pulse width with < 3ns of duration.
Typ.
3.3
3.0
0
Max
3.6
VDD + 0.3
0.8
AC OPERATING CONDITION (TA=-40°C to 85°C, VDD=3.0V to 3.6V, VSS=0V)
Parameter
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
Symbol
VIH / VIL
Vtrip
tR / tF
Voutref
CL
Value
2.4/0.4
1.4
1
1.4
30
Note :
1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF).
For details, refer to AC/DC output load circuit.
2. VDD(min) is 3.15V when HY57V161610ET-7I operates at CAS latency=2 and tCK2=8.9ns
3. VDD(min) of HY57V161610ET-5I/55I is 3.15V‘
Unit
°C
°C
V
V
mA
W
°C ·Sec
Unit Note
V 1, 2, 3
V 1, 4
V 1, 5
Unit Note
V
V
ns
V
pF 1
Rev. 0.1 / Nov. 2003
4

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HY57V161610ET-6I 전자부품, 판매, 대치품
HY57V161610ET-I
AC CHARACTERISTICS (TA=-40°C to 85°C, VDD=3.0V to 3.6V, VSS=0VNote1,2)
Parameter
Symbol
System clock
cycle time
CL=3
CL=2
CL=1
Clock high pulse width
Clock low pulse width
Access time
from clock
CL=3
CL=2
CL=1
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-
time
CLK to data output in high
Z-time
tCK3
tCK2
tCK1
tCHW
tCLW
tAC3
tAC2
tAC1
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ
-5
Min Max
5
-
-
2
2
4.5
1.5
1.5
1
1.5
1
1.5
1
1.5
1
2
25
-55
Min Max
5.5
-
-
2
2
5
2
1.5
1
1.5
1
1.5
1
1.5
1
2
2 5.5
-6
Min Max
6-
10 -
--
2-
2-
- 5.5
-6
--
2-
1.5 -
1-
1.5 -
1-
1.5 -
1-
1.5 -
1-
2-
26
-7
Min Max
7-
10 -
--
2.5 -
2.5 -
-6
-6
--
2.5 -
1.75
-
1-
1.75
-
1-
1.75
-
1-
1.75
-
1-
2-
27
Unit
Note
ns 3
ns 4
ns 4
ns 3
ns
ns 4
ns 4
ns 4
ns 4
ns 4
ns 4
ns 4
ns 4
ns
ns
Rev. 0.1 / Nov. 2003
7

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HY57V161610ET-6I

2 Banks x 512K x 16 Bit Synchronous DRAM

Hynix Semiconductor
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