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부품번호 | NCP1092 기능 |
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기능 | Integrated IEEE 802.3af PoE-PD Interface Controller | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 12 페이지수
NCP1090, NCP1091,
NCP1092
Integrated IEEE 802.3af
PoE-PD Interface Controller
Description
The NCP1090, NCP1091 and NCP1092 are members of
ON Semiconductor’s high power HIPOt Power over Ethernet
Powered Device (PoE−PD) product family and integrate an IEEE
802.3af PoE−PD interface controller.
The 3 variants all incorporate the required functions as such
detection, classification, under voltage lockout, inrush and operational
current limit. A power good signal has been added to guarantee a good
enabling/disabling of the DC−DC controller. In addition, the
NCP1091 offers a programmable under−voltage while the NCP1092
provide an auxiliary pin for applications supporting auxiliary supplies.
The NCP1090, NCP1091 and NCP1092 are fabricated in a robust
high voltage process and integrates a rugged vertical N−channel
DMOS suitable for the most demanding environments and capable of
withstanding harsh environments such as hot swap and cable ESD
events.
The NCP1090, NCP1091 and NCP1092 complement
ON Semiconductor’s ASSP portfolio in industrial devices and can be
combined with stepper motor drivers, CAN bus drivers and other
high−voltage interfacing devices to offer complete solutions to the
industrial and security market.
Features
• Fully Supports IEEE 802.3af Specifications
• Programmable Classification Current
• Adjustable Under Voltage Lock Out (NCP1091 Only)
• Open−Drain Power Good Indicator
• 130 mA Inrush Current Limit
• 500 mA Operational Current Limit
• Pass Switch Disabling Input for Rear Auxiliary Supply Operation
(NCP1092 Only)
• Over−temperature Protection
• Industrial Temperature Range −40°C to 85°C with Full Operation up
to 125°C Junction Temperature
• 0.5 W Hot−swap Pass−switch
• Vertical N−channel DMOS Pass−switch Offers the Robustness of
Discrete MOSFETs
http://onsemi.com
SOIC−8
S SUFFIX
CASE 751AZ
TSSOP−8
T SUFFIX
CASE 948S
PIN CONFIGURATION
1
INRUSH
VPORTP
CLASS
*
DET
PGOOD
VPORTN
RTN
(Top View)
* NCP1090 = NC
NCP1091 = UVLO
NCP1092 = AUX
8
XXXXX
AYWWG
G
1
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP109xxxx
SOIC−8
(Pb−Free)
2500/Tape &
Reel
NCP109xxxx
TSSOP−8
(Pb−Free)
2500/Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
February, 2011 − Rev. 2
1
Publication Order Number:
NCP1090/D
NCP1090, NCP1091, NCP1092
Table 1. PIN DESCRIPTION
Pin No.
Name
NCP1090 NCP1091
INRUSH
1
1
NCP1092
1
CLASS
2
2
2
DET
3
3
3
VPORTN
4
4
4
RTN
5
5
5
PGOOD
6
6
6
NC 7 − −
UVLO
−
7
−
AUX
−
−
7
VPORTP
8
8
8
Type
Output
Output
Output,
Open Drain
Ground
Ground
Output,
Open Drain
−
Input
Input
Input
Description
Current limit programming pin. Connect a resistor between
INRUSH and VPORTN.
Classification current programming pin. Connect a resistor
between CLASS and VPORTN.
Detection pin. Connect a 24.9 kW resistor between DET and
VPORTP for a valid PD detection signature.
Negative input power. Connected to the source of the internal
pass−switch
DC−DC controller power return. Connected to the drain of the
internal pass−switch
Open Drain Power Good Indicator. Pin is in HZ mode when the
power good signal is active.
No connection
Under−voltage lockout input. Voltage with respect to VPORTN.
Connect a resistor−divider from VPORTP to UVLO to
VPORTNx to set an external UVLO threshold.
Auxiliary Pin. When this pin is pulled up, the Pass Switch is
disabled and allows a supply transition from PSE to the rear
auxiliary supply connected between VPORTP and RTN.
Positive input power. Voltage with respect to VPORTN.
Operating Conditions
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max Units
Conditions
VPORTP
Input power supply
−0.3
72
V Voltage with respect to VPORTN
RTN
Analog ground supply 2 −0.3
72
V Pass−switch in off−state (voltage with respect to VPORTN)
CLASS
Analog output
−0.3
72
V Voltage with respect to VPORTN
INRUSH
Analog output
−0.3
3.6
V Voltage with respect to VPORTN
AUX
Analog input
−0.3
72
V Voltage with respect to VPORTN
UVLO
Analog input
−0.3
3.6
V Voltage with respect to VPORTN
PGOOD
Analog output
−0.3
72
V Voltage with respect to RTN
Ta
Ambient temperature −40 85
°C
Tj
Junction temperature
− 125 °C
Tj−TSD
Junction temperature
(Note 1)
− 175 °C Thermal shutdown condition
Tstg
TθJA
Storage Temperature
−55 150
°C
Thermal Resistance,
150 240 °C/W SOIC−8
Junction to Air (Note 2) 160 260
TSSOP−8
ESD−HBM
Human Body Model
2
kV per EIA−JESD22−A114 standard
ESD−CDM Charged Device Model
500
V per ESD−STM5.3.1 standard
ESD−MM
Machine Model
200
V per EIA−JESD22−A115−A standard
LU
Latch−up
±100
mA per JEDEC Standard JESD78
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. Low qJA is obtained with 2S2P test board (2 signal − 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural
convection. Refer to Jedec JESD51 for details.
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4
4페이지 NCP1090, NCP1091, NCP1092
Description of Operation
Powered Device Interface
The integrated PD interface supports the IEEE 802.3af
defined operating modes: detection signature, current
source classification, undervoltage lockout, inrush and
operating current limits. The following sections give an
overview of these previous processes.
Detection
During the detection phase, the incremental equivalent
resistance seen by the PSE through the cable must be in the
IEEE 802.3af standard specification range (23.70 kW to
26.30 kW) for a PSE voltage from 2.7 V to 10.1 V. In order
to compensate for the non−linear effect of the diode bridge
and satisfy the specification at low PSE voltage, the
NCP1090/91/92 present a suitable impedance in parallel
with the 24.9 kW Rdet external resistor. For some types of
diodes (especially Schottky diodes), it may be necessary to
adjust this external resistor.
The Rdet resistor has to be inserted between VPORTP and
DET pins. During the detection phase, the DET pin is pulled
to ground and goes in high impedance mode (open−drain)
once the device exit this mode, reducing thus the current
consumption on the cable.
Classification
Once the PSE device has detected the PD device, the
classification process begins. In classification, the PD
regulates a constant current source that is set by the external
resistor RCLASS value on the CLASS pin. Figure 4 shows
the schematic overview of the classification block. The
current source is defined as:
Iclass
+
9.8 V
Rclass
VPORTP
Class_enable
VPORTP
EN 1.2 V
Under Voltage Lock Out (UVLO)
The NCP1090/91/92 incorporate a fixed under voltage
lock out (ULVO) circuit which monitors the input voltage
and determines when to turn on the pass switch and charge
the dc−dc converter input capacitor before the power up of
the application.
The NCP1091 offers a fixed or adjustable Vuvlo_on
threshold depending if the UVLO pin is used or not. In
Figure 5, the UVLO pin is strapped to ground and the
Vuvlo_on threshold is defined by the internal level.
VPORTP
VPORT
UVLO
VPORTN1,2
Figure 5. Default Internal UVLO Configuration
(NCP1091 only)
To define the UVLO threshold externally, the ULVO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN as shown in
Figure 6.
In order to guarantee the detection signature, the
equivalent input resistor made of the Ruvlo1, Ruvlo2 and
Rdet should be equal to 24.9 kW.
VPORT
Ruvlo1
Rdet
Ruvlo2
VPORTP
DET
UVLO
CLASS
9.8 V
VPORTN
Figure 4. Classification Block Diagram
Power Mode
When the classification hand−shake is completed, the
PSE and PD devices move into the operating mode.
VPORTN1,2
NCP1091
Figure 6. Default Internal UVLO Configuration
(NCP1091 only)
For a Vuvlo_on desired turn−on voltage threshold,
Ruvlo1 and Ruvlo2 can be calculated using the following
equations:
Ruvlo
+
24.9
Rdet
k @ Rdet
* 24.9 k
with
Ruvlo1 ) Ruvlo2 + Ruvlo
and
Ruvlo2
+
1.2
Vuvlo_on
@
Ruvlo
With:
Vuvlo_on: Desired Turn−On voltage threshold
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부품번호 | 상세설명 및 기능 | 제조사 |
NCP1090 | Integrated IEEE 802.3af PoE-PD Interface Controller | ON Semiconductor |
NCP1091 | Integrated IEEE 802.3af PoE-PD Interface Controller | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |