Datasheet.kr   

GS9091B 데이터시트 PDF




Semtech에서 제조한 전자 부품 GS9091B은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 GS9091B 자료 제공

부품번호 GS9091B 기능
기능 270Mb/s Deserializer
제조업체 Semtech
로고 Semtech 로고


GS9091B 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

GS9091B 데이터시트, 핀배열, 회로
GS9091B
GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI
Key Features
• SMPTE 259M-C compliant descrambling and NRZI to
NRZ decoding (with bypass)
• DVB-ASI 8b/10b decoding
• Integrated Cable Equalizer
• 500m typical equalization of Belden 1694A cable
• Integrated line-based FIFO for data alignment/delay,
clock phase interchange, DVB-ASI data packet
extraction and clock rate interchange, and ancillary
data packet extraction
• Integrated VCO and reclocker
• User selectable additional processing features
including:
Š TRS, ANC data checksum, and EDH CRC error
detection and correction
Š programmable ANC data detection
Š illegal code remapping
• Internal flywheel for noise immune H, V, F extraction
• Automatic standards detection and indication
• Enhanced Gennum Serial Peripheral Interface (GSPI)
• JTAG test interface
• Polarity insensitive for DVB-ASI and SMPTE signals
• +1.8V core power supply with optional +1.8V or +3.3V
I/O power supply
• Small footprint (11mm x 11mm)
• Low power operation (typically 350mW)
• Pb-free and RoHS compliant
Applications
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS9091B is a 270Mb/s equalizing and reclocking dese-
rializer with an internal FIFO. It provides a complete re-
ceive solution for SD-SDI and DVB-ASI applications.
In addition to equalizing, reclocking and deserializing the
input data stream, the GS9091B performs NRZI -to-NRZ de-
coding, descrambling as per SMPTE 259M-C, and word
alignment when operating in SMPTE mode. When operat-
ing in DVB-ASI mode, the device will word align the data to
K28.5 sync characters and 8b/10b decode the received
stream.
The integrated equalizer is optimized for 270Mb/s and can
typically equalize up to 500m of Belden 1694A cable. Both
the equalizer and the internal reclocker are fully compati-
ble with both SMPTE and DVB-ASI input streams.
The GS9091B includes a range of data processing functions
such as EDH support (error detection and handling), and
automatic standards detection. The device can also detect
and extract SMPTE 352M payload identifier packets and in-
dependently identify the received video standard. This in-
formation is read from internal registers via the host
interface port.
The GS9091B also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to car-
ry out tasks such as data alignment / delay, clock phase in-
terchange, MPEG packet extraction and clock rate
interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal op-
erating at 27MHz.
The device may also be used in a low-latency data pass
through mode where only descrambling and word align-
ment will be performed in SMPTE mode.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Final Data Sheet
38910 - 3
February 2013
www.semtech.com
1 of 73
Proprietary & Confidential




GS9091B pdf, 반도체, 판매, 대치품
3.7.2 Status Signal Outputs ....................................................................................................... 34
3.8 Data-Through Functionality ...................................................................................................... 34
3.9 Additional Processing Features ................................................................................................ 35
3.9.1 FIFO Load Pulse ................................................................................................................. 35
3.9.2 Ancillary Data Detection and Indication................................................................... 36
3.9.3 EDH Packet Detection...................................................................................................... 37
3.9.4 EDH Flag Detection........................................................................................................... 38
3.9.5 SMPTE 352M Payload Identifier................................................................................... 41
3.9.6 Automatic Video Standard and Data Format Detection ...................................... 42
3.9.7 Error Detection and Indication ..................................................................................... 43
3.9.8 Additional SMPTE Mode Processing ........................................................................... 48
3.10 Internal FIFO Operation ........................................................................................................... 51
3.10.1 Video Mode ....................................................................................................................... 51
3.10.2 DVB-ASI Mode ................................................................................................................. 53
3.10.3 Ancillary Data Extraction Mode ................................................................................ 56
3.10.4 Bypass Mode..................................................................................................................... 58
3.11 Parallel Data Outputs ................................................................................................................. 59
3.11.1 Parallel Data Bus Output Buffers............................................................................... 59
3.11.2 Parallel Output in SMPTE Mode................................................................................. 60
3.11.3 Parallel Output in DVB-ASI Mode............................................................................. 60
3.11.4 Parallel Output in Data-Through Mode................................................................... 60
3.12 Programmable Multi-Function Outputs .............................................................................. 60
3.13 GS9091B Low-latency Mode ................................................................................................... 62
3.14 GSPI Host Interface ..................................................................................................................... 63
3.14.1 Command Word Description ...................................................................................... 63
3.14.2 Data Read and Write Timing ....................................................................................... 64
3.14.3 Configuration and Status Registers........................................................................... 66
3.15 JTAG operation ............................................................................................................................ 67
3.16 Device Power Up ......................................................................................................................... 68
4. References & Relevant Standards ......................................................................................................... 69
5. Application Information .......................................................................................................................... 70
5.1 Typical Application Circuit ........................................................................................................ 70
6. Package & Ordering Information .......................................................................................................... 71
6.1 Package Dimensions ..................................................................................................................... 71
6.2 Packaging Data ............................................................................................................................... 72
6.3 Marking Diagram ........................................................................................................................... 72
6.4 Ordering Information ................................................................................................................... 72
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Final Data Sheet
38910 - 3
February 2013
4 of 73
Proprietary & Confidential

4페이지










GS9091B 전자부품, 판매, 대치품
Table 1-1: Ball List and Description (Continued)
Ball
A10, B10,
C10, D10,
E10, F10,
G10, H10,
J10, K10
B1
B2
B3
B4
B6
B7, J6
B8
Name
DOUT[9:0]
LF-
PLL_VDD
PLL_GND
VCO_GND
FW_EN
CORE_VDD
SMPTE_BYPASS
Timing
Type Description
Synchronous
with RD_CLK
or PCLK
Output
PARALLEL VIDEO DATA BUS
Signal levels are LVCMOS / LVTTL compatible.
When the internal FIFO is enabled and configured for either video
mode or DVB-ASI mode, parallel data will be clocked out of the
device on the rising edge of RD_CLK.
When the internal FIFO is in bypass mode, parallel data will be
clocked out of the device on the rising edge of PCLK.
DOUT9 is the MSB and DOUT0 is the LSB.
Analog
Input
Loop filter component connection. Connect to LF+ through a 4.4nF
capacitor.
Analog
Input
Power
Power supply connection for phase-locked loop. Connect to +1.8V
DC.
Analog
Input
Power
Ground connection for phase-locked loop. Connect to GND.
Analog
Input
Power
Ground connection for Voltage-Controlled-Oscillator. Connect to
GND.
Non
Synchronous
Input
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is
used in the extraction of timing signals, the generation of TRS
signals, the automatic detection of video standards, and in manual
switch line lock handling.
When set LOW, the internal flywheel is disabled. Timing based TRS
errors will not be detected.
Non Input
Synchronous Power
Power supply for digital logic blocks. Connect to +1.8V DC.
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
This pin is an input set by the application layer in Manual mode,
and an output set by the device in Auto mode.
Auto Mode (AUTO/MAN = HIGH):
The SMPTE_BYPASS pin will be HIGH only when the device has
locked to a SMPTE compliant data stream. It will be LOW
otherwise. When the pin is LOW, no I/O processing features are
available.
Manual Mode (AUTO/MAN = LOW):
When the application layer sets this pin HIGH in conjunction with
DVB_ASI = LOW, the device will be configured to operate in SMPTE
mode. All I/O processing features may be enabled in this mode.
When SMPTE_BYPASS is set LOW, the device will not support the
descrambling, decoding, or word alignment of received SMPTE
data. No I/O processing features will be available.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Final Data Sheet
38910 - 3
February 2013
7 of 73
Proprietary & Confidential

7페이지


구       성 총 30 페이지수
다운로드[ GS9091B.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
GS9091B

270Mb/s Deserializer

Semtech
Semtech
GS9091B

270Mb/s Deserializer

Gennum
Gennum

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵