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PDF ISL91107IR Data sheet ( Hoja de datos )
| Número de pieza | ISL91107IR | |
| Descripción | High Efficiency Buck-Boost Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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DATASHEET
High Efficiency Buck-Boost Regulator with 4.1A
Switches
ISL91107IR
The ISL91107IR is a highly-integrated buck-boost switching
regulator that accepts input voltages either above or below the
regulated output voltage. Unlike other buck-boost regulators,
this regulator automatically transitions between operating
modes without significant output disturbance.
This device is capable of delivering up to 2A of output current
(PVIN = 2.8V, VOUT = 3.3V) and provides excellent efficiency
due to its fully synchronous 4-switch architecture. No-load
quiescent current of only 45µA also optimizes efficiency under
light load conditions.
The ISL91107IR is designed for standalone applications and
supports 3.3V fixed output voltages or variable output voltages
with an external resistor divider. Output voltages as low as 1V
or as high as 5.2V are supported using an external resistor
divider.
The ISL91107IR requires only a single inductor and very few
external components. Power supply solution size is minimized
by its 2.5MHz switching frequency, allowing small size external
components.
The ISL91107IR is available in a 3x4 20 Ld TQFN package.
Features
• Accepts input voltages above or below regulated output
voltage
• Automatic and seamless transitions between buck and
boost modes
• Input voltage range: 1.8V to 5.5V
• Output current: up to 2A (PVIN = 2.8V, VOUT = 3.3V)
• High efficiency: up to 96%
• 45µA quiescent current maximizes light load efficiency
• 2.5MHz switching frequency minimizes external component
size
• Selectable forced PWM mode
• Fully protected for short-circuit, over-temperature and
undervoltage
• Small 3mmx4mm TQFN package
Applications
• Smartphones and tablet PCs
• Wireless communication devices
• Optical modules networking equipment
VIN =
1.8V TO 5.5V
C1
22µF
ISL91107IRTNZ
PVIN
LX1
VIN
MODE
EN
LX2
VOUT
FB
SGND PGND
L1
1µH
VOUT = 3.3V
C2
2x22µF
FIGURE 1. TYPICAL ISL91107IRTNZ APPLICATION
100
95 VIN = 3.6V
90
85
80 VIN = 4.2V
75
VIN = 2.7V
VIN = 3V
70
65 VIN = 2.5V
600.001
0.01
0.1
LOAD CURRENT (A)
1.0 3.0
FIGURE 2. EFFICIENCY vs OUTPUT CURRENT (VOUT = 3.3V)
March 2, 2015
FN8687.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL91107IR
Analog Specifications VIN = PVIN = EN = 3.6V, VOUT = 3.3V, L1 = 1µH, C1 = 1x22µF, C2 = 2x22µF, TA = +25°C. Boldface limits apply
across the recommended operating temperature range, -40°C to +85°C and input voltage range (1.8V to 5.5V). (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNITS
SOFT-START and SOFT DISCHARGE
tSS Soft-start Time
Time from when EN signal asserts to when output
voltage ramp starts.
1
ms
Time from when output voltage ramp starts to
1 ms
when output voltage reaches 95% of its nominal
value with device operating in buck mode.
VIN = 4V, IOUT = 200mA
Time from when output voltage ramp starts to
2 ms
when output voltage reaches 95% of its nominal
value with device operating in boost mode.
VIN = 2V, IOUT = 200mA
RDISCHG VOUT Soft-discharge ON-resistance
VIN = 3.6V, EN < VIL
35 Ω
POWER MOSFET
rDSON_P P-channel MOSFET ON-resistance
RDSON_N N-channel MOSFET ON-resistance
IPK_LMT P-channel MOSFET Peak Current Limit
PFM/PWM TRANSITION
VIN = 3.6V
VIN = 3.6V
VIN = 3.6V
55 mΩ
47 mΩ
3.8 4.1 4.8
A
Load Current Threshold, PFM to PWM
Load Current Threshold, PWM to PFM
THERMAL SHUTDOWN
VIN = 3V, VOUT = 3.3V
VIN = 3V, VOUT = 3.3V
375 mA
300 mA
Thermal Shutdown
150 °C
Thermal Shutdown Hysteresis
30 °C
LOGIC INPUTS
ILEAK
Input Leakage
0.05
0.1
µA
VIH Input HIGH Voltage
1.4 V
VIL Input LOW Voltage
0.4 V
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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March 2, 2015
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ISL91107IR
efficiency. In applications where radiated noise must be
minimized, a toroidal or shielded inductor can be used.
TABLE 1. INDUCTOR VENDOR INFORMATION
MANUFACTURER
MFR P/N
DESCRIPTION
Cyntec
PIFE32251B-1R0MS 1µH, 3.2x2.5x1.2mm
TOKO
DFE322512C
1µH, 3.2x2.5x1.2mm
PVIN and VOUT Capacitor Selection
The input and output capacitors should be ceramic X5R type with
low ESL and ESR. The recommended input capacitor value is
22µF, as this would provide adequate RMS current to minimize
the input voltage ripple. A minimum of 10µF is required to
maintain full functionality of the part.
The recommended output capacitor is 2x22µF, 10V, X5R. Note
that the effective value of a ceramic capacitor derates with DC
voltage bias across it. This derating may be up to 70% of the
rated capacitance.
TABLE 2. CAPACITOR VENDOR INFORMATION
MANUFACTURER
PN
DESCRIPTION
Murata
GRM188R61A226ME15D 22µF, 0603, 10V, X5R
TDK C1608X5R1A226M080AC 22µF, 0603, 10V, X5R
Refer to the capacitor datasheet to ensure the combined
effective output capacitance is at least 14µF for proper operation
over the entire recommended load current range. Low output
capacitance may lead to large output voltage drop during load
transient or unstable operation.
Recommended PCB Layout
Correct PCB layout is critical for proper operation of the
ISL91107IR. The following are some general guidelines for the
recommended layout:
1. The input and output capacitors should be positioned as close
to the IC as possible.
2. The ground connections of the input and output capacitors
should be kept as short as possible. The objective is to
minimize the current loop between the ground pads of the
input and output capacitors and the PGND pins of the IC. Use
vias, if required, to take advantage of a PCB ground layer
underneath the regulator.
3. The analog ground pin (SGND) should be connected to a
large/low-noise ground plane on the top or an intermediate
layer on the PCB, away from the switching current path of
PGND. This ensures a low noise signal ground reference.
4. Minimize the trace lengths on the feedback loop to avoid
switching noise pick-up. Vias should be avoided on the
feedback loop to minimize the effect of board parasitic,
particularly during load transients.
5. The LX1 and LX2 traces should be short and must be routed
on the same layer as the IC.
FIGURE 24. RECOMMENDED LAYOUT
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March 2, 2015
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