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PDF HMC7043 Data sheet ( Hoja de datos )
| Número de pieza | HMC7043 | |
| Descripción | 14-Output Fanout Buffer | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Performance, 3.2 GHz, 14-Output
Fanout Buffer
HMC7043
FEATURES
JEDEC JESD204B support
Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)
Very low noise floor: −155.2 dBc/Hz at 983.04 MHz
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency of 3200 MHz
JESD204B-compatible system reference (SYSREF) pulses
25 ps analog and ½ clock input cycle digital delay
independently programmable on each of 14 clock
output channels
SPI-programmable adjustable noise floor vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization
Supports deterministic synchronization of multiple
HMC7043 devices
RFSYNCIN pin or SPI-controlled SYNC trigger for output
synchronization of JESD204B
GPIO alarm/status indicator to determine system health
Clock input to support up to 6 GHz
48-lead, 7 mm × 7 mm LFCSP package
APPLICATIONS
JESD204B clock generation
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Data converter clocking
Phase array reference distribution
Microwave baseband cards
GENERAL DESCRIPTION
The HMC7043 is a high performance clock buffer for the
distribution of ultralow phase noise references for high speed data
converters with either parallel or serial (JESD204B type) interfaces.
The HMC7043 is designed to meet the requirements of multicarrier
GSM and LTE base station designs, and offers a wide range of
clock management and distribution features to simplify baseband
and radio card clock tree designs.
The HMC7043 provides 14 low noise and configurable outputs
to offer flexibility in interfacing with many different components in
a base transceiver station (BTS) system, such as data converters,
local oscillators, transmit/receive modules, field programmable
gate arrays (FPGAs), and digital front-end ASICs. The HMC7043
can generate up to seven DCLK and SYSREF clock pairs per the
JESD204B interface requirements.
The system designer can generate a lower number of DCLK and
SYSREF pairs, and configure the remaining output signal paths
for independent phase and frequency. Both the DCLK and SYSREF
clock outputs can be configured to support different signaling
standards, including CML, LVDS, LVPECL, and LVCMOS, and
different bias conditions to adjust for varying board insertion losses.
One of the unique features of the HMC7043 is the independent
flexible phase management of each of the 14 channels. All
14 channels feature both frequency and phase adjustment. The
outputs can also be programmed for 50 Ω or 100 Ω internal and
external termination options.
The HMC7043 device features an RF SYNC feature that synchro-
nizes multiple HMC7043 devices deterministically, that is, ensures
that all clock outputs start with the same edge. This operation is
achieved by rephrasing the nested HMC7043 or SYSREF control
unit/divider, deterministically, and then restarting the output
dividers with this new phase.
The HMC7043 is offered in a 48-lead, 7 mm × 7 mm LFCSP
package with an exposed pad connected to ground.
FUNCTIONAL BLOCK DIAGRAM
CLKIN/
CLKIN
CLKOUT0
÷ CLKOUT0
SCLKOUT1
SCLKOUT1
RFSYNCIN/
RFSYNCIN
SDATA
SPI
CONTROL
INTERFACE
SYSREF
CONTROL
÷
14-CLOCK
DISTRIBUTION
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
SLEN SCLK
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
HMC7043
Data Sheet
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter
DIGITAL INPUT SIGNALS (RESET, SLEN, SCLK)
Safe Input Voltage Range
Input Load
Input Voltage
Input Logic High
Input Logic Low
SPI Bus Frequency
DIGITAL BIDIRECTIONAL SIGNALS
CONFIGURED AS INPUTS (SDATA, GPIO)
Safe Input Voltage Range
Input Capacitance
Input Resistance
Input Voltage
Input Logic High
Input Logic Low
Input Hysteresis
GPIO ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to
General-Purpose Output (GPO) Driver
DIGITAL BIDIRECTIONAL SIGNALS
CONFIFURED AS OUTPUTS (SDATA, GPIO)
CMOS Mode
Logic 1 Level
Logic 0 Level
Output Drive Resistance (RDRIVE)
Output Driver Delay (tDGPO)
Min
−0.1
1.2
0
−0.1
1.22
0
1.6
Typ Max
+3.6
0.3
VCC
0.5
10
+3.6
0.4
50
VCC
0.24
0.2
2
1.9
0
50
1.5 + 42 × CLOAD
2.2
0.1
Maximum Supported DC Current1
Open-Drain Mode
Logic 1 Level
0.6
3.6
Logic 0 Level
Pull-Down Impedance
Maximum Supported Sink Current1
0.13 0.28
60
5
Unit Test Conditions/Comments
V
pF
V
V
MHz
V
pF
GΩ
V
V
V Occurs around 0.85 V
ns Does not include tDGPO
V
V
Ω
ns Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD
(CLOAD in nF)
mA
External 1 kΩ pull-up resistor
V 3.6 V maximum permitted; specifications set by
external supply
V Against a 1 kΩ external pull-up resistor to 3.3 V
Ω
mA
1 Guaranteed by design and characterization for long-term reliability.
CLOCK INPUT PATH SPECIFICATIONS
Table 4.
Parameter
Min Typ Max Unit Test Conditions/Comments
CLK INPUT (CLKIN) CHARACTERISTICS
Recommended Input Power, AC-Coupled
Differential
−6 +8 dBm
Single-Ended1
−10 +6 dBm Noise floor degrade by 3 dB at fCLKIN = 2400 MHz
Return Loss
−12 dB When terminated with 100 Ω differential
Clock Input Frequency (fCLKIN)
200 3200 MHz Fundamental mode; if <1 GHz, set the low frequency
clock input path enable bit (Register 0x0064, Bit 0)
200 6000 MHz Using clock input ÷ 2
Common-Mode Range
0.4 2.4 V
1 Guaranteed by design and characterization.
Rev. B | Page 4 of 43
5 Page 
HMC7043
Data Sheet
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
Mnemonic
VCC4_CLKIN
RFSYNCIN
RFSYNCIN
VCC5_SYSREF
SLEN
SCLK
SDATA
GPIO
SCLKOUT9
SCLKOUT9
CLKOUT8
CLKOUT8
VCC6_OUT
40 CLKOUT10
41 CLKOUT10
42 SCLKOUT11
43 SCLKOUT11
44 SCLKOUT13
45 SCLKOUT13
46 CLKOUT12
47 CLKOUT12
48 VCC7_OUT
EP
Type1
P
I
I
P
I/O
I/O
I/O
I/O
O
O
O
O
P
O
O
O
O
O
O
O
O
P
Description
Power Supply for the Clock Input Path.
True RF Synchronization Input with Deterministic Delay.
Complementary RF Synchronization Input with Deterministic Delay.
Power Supply for Common SYSREF Divider.
SPI Latch Enable.
SPI Clock.
SPI Data.
Programmable General-Purpose Input/Output.
True Clock Output Channel 9. Default SYSREF profile.
Complementary Clock Output Channel 9. Default SYSREF profile.
True Clock Output Channel 8. Default DCLK profile.
Complementary Clock Output Channel 8. Default DCLK profile.
Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See the
Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 10. Default DCLK profile.
Complementary Clock Output Channel 10. Default DCLK profile.
True Clock Output Channel 11. Default SYSREF profile.
Complementary Clock Output Channel 11. Default SYSREF profile.
True Clock Output Channel 13. Default SYSREF profile.
Complementary Clock Output Channel 13. Default SYSREF profile.
True Clock Output Channel 12. Default DCLK profile.
Complementary Clock Output Channel 12. Default DCLK profile.
Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13. See
the Clock Grouping, Skew, and Crosstalk section.
Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
1 O is output, I is input, P is power, R is reserved, and I/O is input/output.
Rev. B | Page 10 of 43
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HMC7043.PDF ] | |
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