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HMC7043 데이터시트 PDF




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부품번호 HMC7043 기능
기능 14-Output Fanout Buffer
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HMC7043 데이터시트, 핀배열, 회로
Data Sheet
High Performance, 3.2 GHz, 14-Output
Fanout Buffer
HMC7043
FEATURES
JEDEC JESD204B support
Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)
Very low noise floor: −155.2 dBc/Hz at 983.04 MHz
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency of 3200 MHz
JESD204B-compatible system reference (SYSREF) pulses
25 ps analog and ½ clock input cycle digital delay
independently programmable on each of 14 clock
output channels
SPI-programmable adjustable noise floor vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization
Supports deterministic synchronization of multiple
HMC7043 devices
RFSYNCIN pin or SPI-controlled SYNC trigger for output
synchronization of JESD204B
GPIO alarm/status indicator to determine system health
Clock input to support up to 6 GHz
48-lead, 7 mm × 7 mm LFCSP package
APPLICATIONS
JESD204B clock generation
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Data converter clocking
Phase array reference distribution
Microwave baseband cards
GENERAL DESCRIPTION
The HMC7043 is a high performance clock buffer for the
distribution of ultralow phase noise references for high speed data
converters with either parallel or serial (JESD204B type) interfaces.
The HMC7043 is designed to meet the requirements of multicarrier
GSM and LTE base station designs, and offers a wide range of
clock management and distribution features to simplify baseband
and radio card clock tree designs.
The HMC7043 provides 14 low noise and configurable outputs
to offer flexibility in interfacing with many different components in
a base transceiver station (BTS) system, such as data converters,
local oscillators, transmit/receive modules, field programmable
gate arrays (FPGAs), and digital front-end ASICs. The HMC7043
can generate up to seven DCLK and SYSREF clock pairs per the
JESD204B interface requirements.
The system designer can generate a lower number of DCLK and
SYSREF pairs, and configure the remaining output signal paths
for independent phase and frequency. Both the DCLK and SYSREF
clock outputs can be configured to support different signaling
standards, including CML, LVDS, LVPECL, and LVCMOS, and
different bias conditions to adjust for varying board insertion losses.
One of the unique features of the HMC7043 is the independent
flexible phase management of each of the 14 channels. All
14 channels feature both frequency and phase adjustment. The
outputs can also be programmed for 50 Ω or 100 Ω internal and
external termination options.
The HMC7043 device features an RF SYNC feature that synchro-
nizes multiple HMC7043 devices deterministically, that is, ensures
that all clock outputs start with the same edge. This operation is
achieved by rephrasing the nested HMC7043 or SYSREF control
unit/divider, deterministically, and then restarting the output
dividers with this new phase.
The HMC7043 is offered in a 48-lead, 7 mm × 7 mm LFCSP
package with an exposed pad connected to ground.
FUNCTIONAL BLOCK DIAGRAM
CLKIN/
CLKIN
CLKOUT0
÷ CLKOUT0
SCLKOUT1
SCLKOUT1
RFSYNCIN/
RFSYNCIN
SDATA
SPI
CONTROL
INTERFACE
SYSREF
CONTROL
÷
14-CLOCK
DISTRIBUTION
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
SLEN SCLK
Figure 1.
Rev. B
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




HMC7043 pdf, 반도체, 판매, 대치품
Data Sheet
HMC7043
SPECIFICATIONS
VCC = 3.3 V ± 5%, and TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VCC and TA (−40°C to
+85°C) variation, as listed in Table 1.
CONDITIONS
Table 1.
Parameter1
SUPPLY VOLTAGE, VCC
VCC1_CLKDIST
VCC2_OUT
VCC3_OUT
VCC4_CLKIN
VCC5_SYSREF
VCC6_OUT
VCC7_OUT
TEMPERATURE
Ambient Temperature Range, TA
Min Typ Max
3.135 3.3 3.465
3.135 3.3 3.465
3.135 3.3 3.465
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
3.135 3.3 3.465
−40 +25 +85
Unit Test Conditions/Comments
V 3.3 V ± 5%, supply voltage for CLK distribution
V 3.3 V ± 5%, supply voltage for Output Channel 2 and
Output Channel 3
V 3.3 V ± 5%, supply voltage for Output Channel 4, Output
Channel 5, Output Channel 6 and Output Channel 7
V 3.3 V ± 5%, supply voltage for the clock input path
V 3.3 V ± 5%, supply voltage for the common SYSREF divider
V 3.3 V ± 5%, supply voltage for Output Channel 8, Output
Channel 9, Output Channel 10, and Output Channel 11
V 3.3 V ± 5%, supply voltage for Output Channel 0, Output
Channel 1, Output Channel 12, and Output Channel 13
°C
1 Maximum values are guaranteed by design and characterization.
SUPPLY CURRENT
For detailed test conditions, see Table 17 and Table 18.
Table 2
Parameter1, 2
CURRENT CONSUMPTION3
VCC1_CLKDIST
VCC2_OUT4
VCC3_OUT4
VCC4_CLKIN
VCC5_SYSREF
VCC6_OUT4
VCC7_OUT4
Total Current
Min Typ Max Unit Test Conditions/Comments
87 125 mA
90 250 mA Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
52 500 mA Typical value is given at 25°C with two LVDS high performance clocks,
fundamental frequency of the clock input (fO), two SYSREF clocks (off )
16 25 mA Typical value is given at TA = 25°C with RF synchronization (RFSYNC) input
buffer off
23 35 mA Typical value is given at TA = 25°C with internal RF SYNC path off
90 500 mA Typical value is given at 25°C with two LVDS high performance clocks at
divide by 2, two SYSREF clocks (off )
100 500 mA Typical value is given at 25°C with two LVDS clocks at divide by 8, two SYSREF
clocks (off )
458 mA
1 Maximum values are guaranteed by design and characterization.
2 Currents include LVDS termination currents.
3 Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary
synchronization events.
4 Typical specification applies to a normal usage profile (Profile 1 in Table 17) but very low duty cycle currents (sync events) and some optional features are disabled.
This specification assumes output configurations as described in the test conditions/comments column.
Rev. B | Page 3 of 43

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HMC7043 전자부품, 판매, 대치품
HMC7043
Data Sheet
CLOCK OUTPUT DRIVER CHARACTERISTICS
Table 7.
Parameter
CML MODE (LOW POWER)
−3 dB Bandwidth
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Common-Mode Output Voltage
CML MODE (HIGH POWER)
−3 dB Bandwidth
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Differential Output
Voltage Magnitude
Power
Common-Mode Output Voltage
LVPECL MODE
−3 dB Bandwidth
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Differential Output
Voltage Magnitude
Power
Common-Mode Output Voltage
LVDS MODE (LOW POWER)
Maximum Operating Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Common-Mode Output Voltage
Min Typ
Max Unit
Test Conditions/Comments
RL = 100 Ω, 9.6 mA
1950
MHz Differential output voltage = 980 mV p-p diff
175 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
185 ps fCLKOUT = 245.76 MHz, 20% to 80%
145 ps fCLKOUT = 983.04 MHz, 20% to 80%
47.5 50
52.5 %
fCLKOUT = 1075 MHz (2150 MHz/2)
1390
mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1360
mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
VCC − 1.05
V
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
RL = 100 Ω, 14.5 mA
1500
MHz Differential output voltage = 1470 mV p-p diff
250 ps fCLKOUT = 245.76 MHz, 20% to 80%
165 ps fCLKOUT = 983.04 MHz, 20% to 80%
255 ps fCLKOUT = 245.76 MHz, 20% to 80%
170 ps fCLKOUT = 983.04 MHz, 20% to 80%
47.5 50
52.5 %
fCLKOUT = 1075 MHz (2150 MHz/2)
2000
mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1800
mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
590 mV p-p diff fCLKOUT = 3200 MHz
−3.6
dBm diff
fCLKOUT = 3200 MHz
VCC − 1.6
V
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
RL = 150 Ω, 4.8 mA
2400
MHz Differential output voltage = 1240 mV p-p diff
135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130 ps fCLKOUT = 983.04 MHz, 20% to 80%
135 ps fCLKOUT = 245.76 MHz, 20% to 80%
130 ps fCLKOUT = 983.04 MHz, 20% to 80%
47.5 50
52.5 %
fCLKOUT = 1075 MHz (2150 MHz/2)
1760
mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1850
mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
930 mV p-p diff fCLKOUT = 3200 MHz
0.3
dBm diff
fCLKOUT = 3200 MHz
VCC − 1.3
V
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1.75 mA
1700
MHz Differential output voltage = 320 mV p-p diff
135 ps fCLKOUT = 245.76 MHz, 20% to 80%
100 ps fCLKOUT = 983.04 MHz, 20% to 80%
135 ps fCLKOUT = 245.76 MHz, 20% to 80%
95 ps fCLKOUT = 983.04 MHz, 20% to 80%
47.5 50
52.5 %
fCLKOUT = 1075 MHz (2150 MHz/2)
390 mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1.1 V fCLKOUT = 245.76 MHz (2949.12 MHz/12)
Rev. B | Page 6 of 43

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