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GD25LQ128C 데이터시트 PDF




ELM에서 제조한 전자 부품 GD25LQ128C은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 GD25LQ128C 자료 제공

부품번호 GD25LQ128C 기능
기능 1.8V Uniform Sector Dual and Quad Serial Flash
제조업체 ELM
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GD25LQ128C 데이터시트, 핀배열, 회로
http://www.elm-tech.com
GD25LQ128C
DATASHEET




GD25LQ128C pdf, 반도체, 판매, 대치품
GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash
1. FEATURES
http://www.elm-tech.com
128M-bit Serial Flash
Program/Erase Speed
- 16384K-byte
- 256 bytes per programmable page
Standard, Dual, Quad SPI, QPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
- QPI: SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
- 133MHz for fast read with 30PF load
- Dual I/O Data transfer up to 266Mbits/s
- Quad I/O Data transfer up to 532Mbits/s
- QPI Mode Data transfer up to 532Mbits/s
- Continuous Read With 8/16/32/64-byte Wrap
Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# pin
- Top or Bottom, Sector or Block selection
- Page Program time: 0.7ms typical
- Sector Erase time: 90ms typical
- Block Erase time: 0.3/0.5s typical
- Chip Erase time: 100s typical
Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
- Erase/Program Suspend/Resume
Low Power Consumption
- 20mA maximum active current
- 5μA maximum power down current
Advanced security Features
- 64-Bit Customer ID
- 3*512-Byte Security Registers With OTP Lock
Single Power Supply Voltage
- Full voltage range: 1.65~2.0V
♦ Minimum 100,000 Program/Erase Cycles
62 - 4
Rev.1.0

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GD25LQ128C 전자부품, 판매, 대치품
GD25LQ128CxIGx 1.8V Uniform Sector Dual and Quad Serial Flash
4. DEVICE OPERATION
http://www.elm-tech.com
SPI Mode
Standard SPI
The GD25LQ128C feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data
is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25LQ128C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1.
Quad SPI
The GD25LQ128C supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O
Fast Read”, “Quad I/O Word Fast Read” “Quad Page Program” (6BH, EBH, E7H, 32H) commands. These
commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When
using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and
HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in
Status Register to be set.
QPI
The GD25LQ128C supports Quad Peripheral Interface (QPI) operations only when the device is switched
ftom Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI
mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are
exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)”
commands are used to switch between these two modes. Upon power-up and after software reset using “Reset
(99H)” command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the
non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation
of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high
during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the
HOLD# must be at high and then CS# must be at low.
62 - 7
Rev.1.0

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관련 데이터시트

부품번호상세설명 및 기능제조사
GD25LQ128C

1.8V Uniform Sector Dual and Quad Serial Flash

ELM
ELM
GD25LQ128C

1.8V Uniform Sector Dual and Quad Serial Flash

GigaDevice
GigaDevice

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