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GD25Q128C 데이터시트 PDF




ELM에서 제조한 전자 부품 GD25Q128C은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 GD25Q128C 자료 제공

부품번호 GD25Q128C 기능
기능 3.3V Uniform Sector Dual and Quad Serial Flash
제조업체 ELM
로고 ELM 로고


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GD25Q128C 데이터시트, 핀배열, 회로
http://www.elm-tech.com
GD25Q128C
DATASHEET




GD25Q128C pdf, 반도체, 판매, 대치품
GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
1. FEATURES
http://www.elm-tech.com
128M-bit Serial Flash
Program/Erase Speed
- 16384K-byte
- 256 bytes per programmable page
Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/RESET#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/RESET#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
- QPI: SCLK, CS#, IO0, IO1, IO2, IO3
- Page Program time: 0.6ms typical
- Sector Erase time: 50ms typical
- Block Erase time: 0.2/0.3s typical
- Chip Erase time: 60s typical
Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
High Speed Clock Frequency
Low Power Consumption
- 104MHz for Standard and Dual SPI fast read with 30PF load - 20mA maximum active current
- 80MHz for Quad SPI and QPI fast read with 30PF load - 5μA maximum power down current
- Dual I/O Data transfer up to 208Mbits/s
- Quad I/O Data transfer up to 320Mbits/s
- QPI Mode Data transfer up to 320Mbits/s
- Continuous Read With 8/16/32/64-byte Wrap
Advanced Security Features(1)
- 3×512-Byte Security Registers With OTP Locks
- Discoverable parameters(SFDP) register
Software/Hardware Write Protection
Single Power Supply Voltage
- Write protect all/portion of memory via software
- Full voltage range: 2.7~3.6V
- Enable/Disable protection with WP# pin
- Top or Bottom, Sector or Block selection
Cycling endurance
♦ Package Information
- SOP8 (208mil)
- WSON8 (6×5mm)
- Minimum 100,000 Program/Erase Cycles
Data retention
- 20-year data retention typical.
Note: (1) Please contact ELM for details.
69 - 4
Rev.1.2

4페이지










GD25Q128C 전자부품, 판매, 대치품
GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
4. DEVICE OPERATION
http://www.elm-tech.com
SPI Mode
Standard SPI
The GD25Q128C feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q128C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1.
Quad SPI
The GD25Q128C supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast
Read”, “Quad I/O Word Fast Read”(6BH, EBH, E7H) commands. These commands allow data to be transferred
to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and
SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD#/RESET# pins become IO2 and IO3.
Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
QPI
The GD25Q128C supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI
mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are
exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)”
commands are used to switch between these two modes. Upon power-up and after software reset using “Reset
(99H)” command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the
non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the
hardware pin for 8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the HOLD# function is only
available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as dedicated data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation
of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during
HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD#
must be at high and then CS# must be at low.
69 - 7
Rev.1.2

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