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CY14V101PS 데이터시트 PDF




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부품번호 CY14V101PS 기능
기능 1-Mbit (128K x 8) Quad SPI nvSRAM
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CY14V101PS 데이터시트, 핀배열, 회로
CY14V101PS
1-Mbit (128K × 8) Quad SPI nvSRAM
with Real Time Clock
Features
Density
1 Mbit (128K × 8)
Bandwidth
108-MHz high-speed interface
Read and write at 54 MBps
Serial Peripheral Interface
Clock polarity and phase modes 0 and 3
Multi I/O option – Single SPI (SPI), Dual SPI (DPI), and Quad
SPI (QPI)
High reliability
Infinite read, write, and RECALL cycles
One million STORE cycles to nonvolatile elements (SONOS
FLASH Quantum trap)
Data retention: 20 years at 85 °C
Read
Commands: Standard, Fast, Dual I/O, and Quad I/O
Modes: Burst Wrap, Continuous (XIP)
Write
Commands: Standard, Fast, Dual I/O, and Quad I/O
Modes: Burst Wrap
Data protection
Hardware: Through Write Protect Pin (WP)
Software: Through Write Disable instruction
Block Protection: Status Register bits to control protection
Special instructions
STORE/RECALL: Transfer data between SRAM and
Quantum Trap nvSRAM
Serial Number: 8-byte customer selectable (OTP)
Identification Number: 4-byte Manufacturer ID and Product
ID
Store from SRAM to nonvolatile SONOS FLASH Quantum Trap
AutoStore: Initiated automatically at power-down with a small
capacitor (VCAP)
Software: Using SPI instruction (STORE)
Hardware: HSB pin
Recall from nonvolatile SONOS FLASH Quantum Trap to
SRAM
Auto RECALL: Initiated automatically at power-up
Software: Using SPI instruction (RECALL)
Low-power modes
Sleep: Average current = 380 µA at 85 °C
Hibernate: Average current = 8 µA at 85 °C
Operating supply voltages
Core VCC: 2.7 V to 3.6 V
I/O VCCQ: 1.71 V to 2.0 V
Temperature range
Industrial: –40 °C to 85 °C
Packages
16-pin SOIC
Functional Overview
The Cypress CY14V101PS combines a 1-Mbit nvSRAM with a
QPI interface. The QPI allows writing and reading the memory in
either a single (one I/O channel for one bit per clock cycle), dual
(two I/O channels for two bits per clock cycle), or quad (four I/O
channels for four bits per clock cycle) through the use of selected
opcodes.
The memory is organized as 128 Kbytes each consisting of
SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The
SRAM provides infinite read and write cycles, while the
nonvolatile cells provide highly reliable storage of data. Data
transfers from SRAM to the nonvolatile cells (STORE operation)
take place automatically at power-down. On power-up, data is
restored to the SRAM from the nonvolatile cells (RECALL
operation). The user can initiate the STORE and RECALL
operations through SPI instructions.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-94176 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 19, 2016




CY14V101PS pdf, 반도체, 판매, 대치품
CY14V101PS
Pinout
Pin Definitions
Pin Name
NC (I/O3)
VCCQ
VCC
CS
SO (I/O1)
WP (I/O2)
VSS
HSB
VCAP
VRTCbat
Xout
Xin
Figure 1. 16-pin SOIC Pinout
NC (I/O3)
VCC
VRTCBAT
XOUT
XIN
RFU
CS
SO (I/O1)
1
2
3
4
5
6
7
8
16- pin
SOIC
Top View
16
15
14
13
12
11
10
9
SCK
SI (I/O0)
VCCQ
VCAP
HSB
INT/ SDQW
VSS
WP (I/O2)
Input
I/O Type
Input/Output
Power Supply
Power Supply
Input
Output
Input/Output
Input
Input/Output
Ground
Input/Output
Power Supply
Power supply
Output
Input
Description
Not connected. In Single or Dual mode, this pin is not connected and left
floating. These two modes do not support QSPI instructions.
I/O3: When the part is in Quad mode, the NC (I/O3) pin becomes I/O3 pin
and acts as input/output.
In Quad mode supporting SPI/DPI instructions, this pin needs to be tri-stated
while CS is enabled.
Power supply for the I/Os of the device.
Power supply to the core of the device.
Chip Select. Activates the device when pulled LOW. Driving this pin HIGH
puts the device in standby state.
Serial Output. Pin for output of data through SPI.
I/O1: When the part is in dual or quad mode, the SO (I/O1) pin becomes
I/O1 pin and acts as input/output.
Write Protect. Implements hardware write-protection in SPI/DPI modes.
I/O2: When the part is in quad mode, the WP (I/O2) pin becomes an I/O2
pin and acts as input/output.
Power supply ground to the core and I/Os of the device.
Hardware STORE Busy:
Output: Indicates the busy status of nvSRAM when LOW. After each
Hardware and Software STORE operation, HSB is driven HIGH for a short
time (tHHHD) with standard output HIGH current and then a weak internal
pull-up resistor keeps this pin HIGH (external pull-up resistor connection is
optional).
Input: Hardware STORE can be initiated by pulling this pin LOW externally.
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to
STORE data from the SRAM to nonvolatile elements. If AutoStore is not
needed, this pin must be left as No Connect. It must never be connected to
ground.
Battery backup for RTC.
Crystal output connection. Left unconnected if RTC feature is not used.
Crystal input connection. Left unconnected if RTC feature is not used.
Document Number: 001-94176 Rev. *I
Page 4 of 67

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CY14V101PS 전자부품, 판매, 대치품
CY14V101PS
Note If a capacitor is not connected to the VCAP pin, AutoStore
must be disabled by issuing the AutoStore Disable instruction
(Autostore Disable (ASDI) Instruction on page 44). If AutoStore
is enabled without a capacitor on the VCAP pin, the device
attempts AutoStore without sufficient charge to complete the
operation. This will corrupt the data stored in the memory array
along with the serial number and Status Register. Updating them
will be required to resume normal functionality.
Figure 2 shows the connection of the storage capacitor (VCAP)
for AutoStore operation. Refer to on page 55 for the size of the
VCAP.
Figure 2. AutoStore Mode
VCCQ VCC
0.1uF
VCCQ
VCC
0.1uF
CS VCAP
VSS
VCAP
Software STORE Operation
Software STORE allows an instruction-based STORE operation.
It is initiated by executing a STORE instruction, irrespective of
whether a write has been previously performed.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The WIP bit of
the Status Register or the HSB pin may be polled to find the
Ready or Busy status. After the tSTORE cycle time is completed,
the nvSRAM is ready for normal operations.
Hardware STORE and HSB Pin Operation
The HSB pin in the device is a dual-purpose pin used to either
initiate a STORE operation or to poll STORE/RECALL
completion status. If a STORE or RECALL is not in progress, the
HSB pin can be driven low to initiate a Hardware STORE cycle.
Detecting a low on HSB, nvSRAM will start a STORE operation
after tDELAY duration. A hardware STORE cycle is only possible
if a SRAM write operation has been performed since the last
STORE/RECALL cycle. This allows for optimizing the SONOS
FLASH endurance cycles. All reads and writes to the memory
are inhibited for tSTORE duration. The HSB pin also acts as an
open drain driver (internal 100-kweak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE/RECALL is in progress.
Note After each Hardware and Software STORE operation, HSB
is driven HIGH for a short time (tHHHD) with standard output
HIGH current and then remains HIGH by an internal 100-k
pull-up resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Note It is recommended to perform a Hardware STORE only
when the device is in Standby state. Execute-in-place (XIP)
should be exited as well.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
cells to the SRAM cells. A RECALL may be initiated in two ways:
Hardware RECALL, initiated on power-up and Software
RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared (set to ‘0’). Next, the nonvolatile information is
transferred into the SRAM cells. All memory accesses are
inhibited while a RECALL cycle is in progress. The RECALL
operation does not alter the data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile cells to the SRAM cells.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. The HSB pin is used
to detect the ready status of the device.
Software RECALL
Software RECALL allows you to initiate a RECALL operation to
restore the content of the nonvolatile memory to the SRAM. A
Software RECALL is issued by using the RECALL instruction.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDI instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re-enabled by using the ASEN instruction.
However, ASEN and ASDI operations require a STORE
operation to make them nonvolatile.
Note The device has AutoStore enabled and 0x00 written to all
cells from the factory.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power-Up RECALL operation cannot
be disabled.
Document Number: 001-94176 Rev. *I
Page 7 of 67

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CY14V101PS

1-Mbit (128K x 8) Quad SPI nvSRAM

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