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PE4312 데이터시트 PDF




Peregrine Semiconductor에서 제조한 전자 부품 PE4312은 전자 산업 및 응용 분야에서
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부품번호 PE4312 기능
기능 RF Digital Step Attenuator
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PE4312 데이터시트, 핀배열, 회로
Product Description
The PE4312 is a 50, HaRP™ technology-enhanced 6-bit
RF Digital Step Attenuator (DSA) designed for use in 3G/4G
wireless infrastructure and other high performance RF
applications.
This DSA is a pin-compatible upgraded version of the
PE4302 with higher linearity, improved attenuation accuracy
and faster switching speed. An integrated digital control
interface supports both serial and parallel programming of
the attenuation, including the capability to program an initial
attenuation state at power-up.
Covering a 31.5 dB attenuation range in 0.5 dB steps, it
maintains high linearity and low power consumption from
1 MHz through 4 GHz. PE4312 also features an external
negative supply option, and is offered in a 20-lead 4 × 4 mm
QFN package. In addition, no external blocking capacitors
are required if 0 VDC is present on the RF ports.
The PE4312 is manufactured on Peregrine’s UltraCMOS®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver high
linearity and excellent harmonics performance. It is an
innovative feature of the UltraCMOS® process, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Figure 1. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
Parallel Control 6
Serial Control 3
Power-Up Control 2
Control Logic Interface
DOC-02132
Product Specification
PE4312
UltraCMOS® RF Digital Step Attenuator
6-bit, 31.5 dB, 1 MHz–4 GHz
Features
 Attenuation: 0.5 dB steps to 31.5 dB
 Safe attenuation state transitions
 Monotonicity: 0.5 dB up to 4 GHz
 High attenuation accuracy
 ±(0.10 + 1% x Atten) @ 1 GHz
 ±(0.15 + 2% x Atten) @ 2.2 GHz
 ±(0.15 + 8% x Atten) @ 4 GHz
 High linearity: +59 dBm IIP3
 Wide power supply range of 2.3–5.5V
 1.8V control logic compatible
 105 °C operating temperature
 Programming modes
 Direct parallel
 Latched parallel
 Serial
 Unique power-up state selection
 Pin compatible to PE4302, PE4305
and PE4306
Figure 2. Package Type
20-lead 4 × 4 mm QFN
Document No. DOC-13514-6 www.psemi.com
©2013-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13




PE4312 pdf, 반도체, 판매, 대치품
PE4312
Product Specification
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Switching Frequency
The PE4312 has a maximum 25 kHz switching
rate in normal mode (pin 12 = GND). A faster
switching rate is available in bypass mode (pin 12
= VSS_EXT). The rate at which the PE4312 can be
switched is then limited to the switching time as
specified in Table 1.
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
Safe Attenuation State Transitions
The PE4312 features a novel architecture to
provide safe transition behavior when changing
attenuation states. When RF input power is
applied, positive output power spikes are
prevented during attenuation state changes by
optimized internal timing control.
Resistor on Pin 1 & 3
A 10 kresistor on the inputs to pin 1 and 3 (see
Figure 26) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
Moisture Sensitivity Level
The moisture sensitivity level rating for the
PE4312 in the 4 × 4 mm QFN package is MSL1.
Spurious Performance
The typical low-frequency spurious performance
of the PE4312 in normal mode is –140 dBm
(pin 12 = GND). If spur-free performance is
desired, the internal negative voltage generator
can be disabled by applying a negative voltage to
VSS_EXT (pin 12).
Figure 4. Power Derating Curve for 1–50 MHz
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
0
RF Input Power, CW or Pulsed (40C to 105C)
5 10 15 20 25 30 35 40 45 50
Frequency (MHz)
©2013-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 13
Document No. DOC-13514-6 UltraCMOS® RFIC Solutions

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PE4312 전자부품, 판매, 대치품
PE4312
Product Specification
Typical Performance Data @ 25 °C and VDD = 3.3V, unless otherwise noted
Figure 7. Insertion Loss vs Frequency
@ Major Attenuation Steps
Figure 8. Insertion Loss vs Temperature
0
-5
-10
-15
-20
-25
-30
-35
-40
0
0 dB
0.5 dB
0.5 1
1 dB
2 dB
4 dB
8 dB
16 dB
31.5 dB
1.5 2 2.5 3 3.5 4
Frequency (GHz)
0
-0.5
-1
-1.5
-2
-2.5
0
-55C -40C 25C 85C 105C
0.5 1 1.5 2 2.5 3 3.5
Frequency (GHz)
4
Figure 9. Input Return Loss vs Frequency
@ Major Attenuation Steps
0
5
10
15
20
25
30
35
40
45
0
0 dB 0.5 dB
0.5 1
1 dB 2 dB 4 dB 8 dB 16 dB 31.5 dB
1.5 2 2.5 3 3.5 4
Frequency (GHz)
Figure 11. Output Return Loss vs Frequency
@ Major Attenuation Steps
0 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.5 dB
0
-10
-20
-30
-40
-50
-60
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (GHz)
Figure 10. Input Return Loss vs Temperature
0
5
10
15
20
25
0
55C 40C 25C 85C 105C
0.5 1 1.5 2 2.5 3 3.5
Frequency (GHz)
4
Figure 12. Output Return Loss vs Temperature
0
5
10
15
20
25
0
55C 40C 25C 85C 105C
0.5 1 1.5 2 2.5 3 3.5
Frequency (GHz)
4
Document No. DOC-13514-6 www.psemi.com
©2013-2016 Peregrine Semiconductor Corp. All rights reserved.
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