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PDF PE43705 Data sheet ( Hoja de datos )
| Número de pieza | PE43705 | |
| Descripción | RF Digital Step Attenuator | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
The PE43705 is a 50Ω, HaRP™ technology-enhanced, 7-bit
RF Digital Step Attenuator (DSA) designed for use in 3G/4G
wireless infrastructure and other high performance RF
applications.
This DSA is a pin-compatible upgraded version of PE43703
with higher power handling and a wider frequency, control
voltage and operating temperature range. An integrated
digital control interface supports both Serial and Parallel
programming of the attenuation, including the capability to
program an initial attenuation state at power-up.
Covering a 31.75 dB attenuation range in 0.25 dB, 0.50 dB,
or 1 dB steps, it maintains a monotonic step response from
50 MHz through 8 GHz. PE43705 also features safe
attenuation state transitions and is offered in a 32-lead
5x5 mm QFN package. In addition, no external blocking
capacitors are required if 0V DC is present on the RF ports.
The PE43705 is manufactured on Peregrine’s UltraCMOS®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver high
linearity and excellent harmonics performance. It is an
innovative feature of the UltraCMOS process, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Figure 1. Functional Diagram
Product Specification
PE43705
UltraCMOS® RF Digital Step
Attenuator, 7-bit, 31.75 dB
50 MHz – 8 GHz
Features
• Attenuation options: covers a 31.75 dB
range in 0.25 dB, 0.5 dB, or 1.0 dB steps
• 0.25 dB monotonicity for ≤ 6 GHz
• 0.50 dB monotonicity for ≤ 7 GHz
• 1.00 dB monotonicity for ≤ 8 GHz
• Safe attenuation state transitions
• High power handling
• 31 dBm, Pulsed @ 8 GHz
• 28 dBm, CW @ 8 GHz
• High linearity: +58 dBm IIP3
• 1.8V control logic compatible
• 105°C operating temperature
• Programming modes
• Direct Parallel
• Latched Parallel
• Serial
• Serial Addressable
• High-attenuation state @ power-up (PUP)
• ESD performance
• 1.5 kV HBM on all pins
Figure 2. Package Type
32-lead 5x5 mm QFN
Document No. DOC-47814-3 | www.psemi.com
71-0052
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 18
1 page  
PE43705
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Pin Descriptions
Pin # Pin Name
Description
1 N/C No connect
2 VDD Supply voltage
3 P/S Serial/Parallel mode select
4 A0 Address bit A0 connection
5, 6,
8-17, 19,
20
7
18
GND
RF11
RF21
Ground
RF1 port (RF input)
RF2 port (RF output)
21 A2 Address bit A2 connection
22 A1 Address bit A1 connection
23 LE Serial interface latch enable input
24
CLK
Serial interface clock input
25 SI Serial interface data input
26 C16 (D6)2 Parallel control bit, 16 dB
27 C8 (D5)2 Parallel control bit, 8 dB
28 C4 (D4)2 Parallel control bit, 4 dB
29 C2 (D3)2 Parallel control bit, 2 dB
30 C1 (D2)2 Parallel control bit, 1 dB
31 C0.5 (D1)2 Parallel control bit, 0.5 dB
32 C0.25 (D0)2 Parallel control bit, 0.25 dB
Pad
GND
Exposed pad: ground for proper operation
Notes: 1. RF pins 7 and 18 must be at 0V DC. The RF pins do not require DC
blocking capacitors for proper operation if the 0V DC
requirement is met
2. Ground C0.25, C0.5, C1 C2, C4, C8, C16 if not in use
Table 5. Operating Ranges
Parameter
Symbol Min Typ
Supply voltage
VDD 2.3
Supply current IDD 130
Digital input high
VIH 1.17
Digital input low
VIL –0.3
Digital input current
ICTRL
RF input power, CW
PMAX,CW
RF input power, pulsed1 PMAX,PULSED
Operating temperature
range
TOP
-40
Note 1: Pulsed, 2.5% duty cycle of 4620 µs period, 50Ω
Max Unit
5.5 V
200 μA
3.6 V
0.6 V
15 μA
+28 dBm
+31 dBm
+105 °C
Table 6. Absolute Maximum Ratings
Parameter/Condition
Symbol Min
Max
Supply voltage
Digital input voltage
Maximum input power
Storage temperature range
ESD voltage HBM1, all pins
ESD voltage MM2, all pins
VDD
VCTRL
PMAX,ABS
TST
VESD,HBM
-0.3
-0.3
-65
VESD,MM
5.5
3.6
+34
150
1500
200
ESD voltage CDM3, all pins VESD,CDM
250
Notes: 1. Human Body Model (MIL-STD 883 Method 3015)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model (JEDEC JESD22-C101)
Unit
V
V
dBm
°C
V
V
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Document No. DOC-47804-3 | www.psemi.com
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 18
5 Page 
PE43705
Product Specification
Typical Performance Data, 0.5 dB Step @ 25°C and VDD = 3.3V unless otherwise specified
Figure 10. 0.5 dB Step Attenuation vs. Frequency*
0.5
0.25
0.2GHz
0.9GHz
1.8GHz
0 2.2GHz
3GHz
4GHz
-0.25
5GHz
6GHz
7GHz
-0.5
0 4 8 12 16 20 24 28 32
Attenuation Setting (dB)
* Monotonicity is held so long as step-attenuation does not cross below –0.5 dB
Figure 11. 0.5 dB Step, Actual vs. Frequency
35
30
25 0.9GHz
1.8GHz
20
2.2GHz
15 3GHz
4GHz
10
5GHz
5 6GHz
0 7GHz
0 4 8 12 16 20 24 28 32
Ideal Attenuation (dB)
Figure 12. 0.5 dB Major State Bit Error vs.
Attenuation Setting
1.5
1 0.5dB
1dB
0.5 2dB
4dB
8dB
0
16dB
31.5dB
-0.5
01234567
Frequency (GHz)
Figure 13. 0.5 dB Attenuation Error vs.
Frequency
1.5
1
0.5
0
-0.5
0 4 8 12 16 20 24 28 32
Attenuation Setting (dB)
0.2GHz
0.9GHz
1.8GHz
2.2GHz
3GHz
4GHz
5GHz
6GHz
7GHz
Document No. DOC-47804-3 | www.psemi.com
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet PE43705.PDF ] | |
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