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MUX8562 데이터시트 PDF




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부품번호 MUX8562 기능
기능 Dual 16-Channel Analog Multiplexer Module
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MUX8562 데이터시트, 핀배열, 회로
Standard Products
MUX8562 Dual 16-Channel Analog Multiplexer Module
+5V, Radiation Tolerant
www.aeroflex.com/mux
Preliminary
December 7, 2009
FEATURES
32-channels provided by two independent 16-channel multiplexers
Single +5V power supply
Radiation performance
- Total dose:
- SEU:
150 krads(Si), Dose rate = 50 - 300 rads(Si)/s
Immune up to 90 MeV-cm2/mg
- SEL:
Immune by process design
Full military temperature range
Low power consumption < 5mW
CMOS analog switching allows rail to rail operation and low switch impedance
Separate address (A0-3 & B0-3) and enable (EN0-15 & EN16-31) for CH0-15 and CH16-31
Fast access time < 500ns typical
Break-Before-Make switching
High analog input impedance (power on or off )
Designed for aerospace and high reliability space applications
Packaging – Hermetic ceramic
- 56 leads, 0.80"Sq x 0.20"Ht quad flat pack
- Typical Weight 6 grams
DSCC SMD 5962-10209 pending
Note: Aeroflex Plainview does not currently have a DSCC certified Radiation Hardened Assurance Program.
GENERAL DESCRIPTION
Aeroflex’s MUX8562 is a radiation tolerant +5V only Dual 16 channel multiplexer MCM (Multi Chip
Module).
The MUX8562 has been specifically designed to meet exposure to radiation environments. It is available in
a 56 lead High Temperature Co-Fired Ceramic (HTCC) Quad Flatpack (CQFP). It is guaranteed
operational from -55°C to +125°C. Available screened in accordance with MIL-PRF-38534, the
MUX8562 is ideal for demanding military and space applications.
ORGANIZATION AND APPLICATION
The MUX8562 consists of two independent 16 channel +5V only multiplexers arranged as shown in the
block diagram.
A Section
Sixteen (16) channels addressable by bus A0~A3, enabled by EN0-15 and outputted on Output1(0-15).
B Section
Sixteen (16) channels addressable by bus B0~B3, enabled by EN16-31 and outputted on Output2(16-31).
SCD8562 Rev A




MUX8562 pdf, 반도체, 판매, 대치품
DC ELECTRICAL PERFORMANCE CHARACTERISTICS 1/ (continued)
(TC = -55°C to +125°C, +VEE = +5V, VREF = +5.0V - Unless otherwise specified)
Parameter
Positive Input Leakage
Current CH0-CH31
Negative Input Leakage
Current CH0-CH31
Positive Output
Leakage Current
OUTPUTS (pins 12,45)
Switch ON Resistance
OUTPUTS
(pins 12,45) 6/
Symbol
+ISOFFOUTPUT(ALL)
-ISOFFOUTPUT(ALL)
+IDOFFOUTPUT(ALL)
RDS(ON)(0-31)A
Conditions
VIN = +5V, VEN = 4V, output and all unused MUX inputs
under test = 0V 2/, 3/
VIN = 0V, VEN = 4V, output and all unused MUX inputs
under test = +5V 2/, 3/
VOUT = +5V, VEN = 4V, and inputs grounded except
channel being tested. 3/, 4/
VIN = +5V, VEN = 0.8V, IOUT = -1mA 2/, 3/, 5/
Min Max Units
-100 +100 nA
-100 +100 nA
-50 +1500 nA
50 1000 Ω
Notes:
1/ Measure inputs sequentially. Ground all unused inputs of the device under test. VA is the applied input voltage to the address lines A(0-3). VB is
the applied input voltage to the address lines B(0-3).
2/ VIN is the applied input voltage to the input channels CH0-CH31.
3/ VEN is the applied input voltage to the enable line EN (0-15) and EN (16-31)
4/ VOUT is the applied input voltage to the output lines OUTPUT1 (0-15), OUTPUT2 (16-31)
5/ Negative current is the current flowing out of each of the MUX pins. Positive current is the current flowing into each MUX pin.
6/ The MUX8562 cannot be operated with analog inputs below 0 volts.
7/ Not tested, guaranteed to the specified limits.
SWITCHING CHARACTERISTICS
((TC = -55°C TO +125°C, +VEE = +5V, VREF = +5.0V - UNLESS OTHERWISE SPECIFIED))
Parameter
Switching Test MUX
Symbol
tAHL
tALH
tONEN
tOFFEN
Conditions
RL = 10KΩ, CL = 50pF
RL = 1KΩ, CL = 50pF
Min Max
100 700
100 700
100 700
100 700
Units
ns
ns
ns
ns
SCD8562 Rev A Preliminary 12/07/09
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MUX8562 전자부품, 판매, 대치품
PIN NUMBERS & FUNCTIONS
MUX8562 – 56 Leads Ceramic QUAD Flat Pack
Pin #
Function
Pin #
Function
1 CH0
29 CH31
2 CH1
30 CH30
3 CH2
31 CH29
4 CH3
32 CH28
5 CH4
33 CH27
6 CH5
34 CH26
7 GND
35 GND
8 GND
36 GND
9 CH6
37 CH25
10 CH7
38 CH24
11 CASE GND
39 VREF
12
OUTPUT1 (0-15)
40
B3
13 EN 0-15
41 B2
14 A0
42 B1
15 A1
43 B0
16 A2
44 EN 16-31
17 A3
45 OUTPUT2 (16-31)
18 +VEE
46 GND
19 CH15
47 CH16
20 CH14
48 CH17
21 GND
49 GND
22 GND
50 GND
23 CH13
51 CH18
24 CH12
52 CH19
25 CH11
53 CH20
26 CH10
54 CH21
27 CH9
55 CH22
28 CH8
56 CH23
Notes:
1. Package lid is internally connected to circuit ground (Pins 7, 8, 11, 21, 22, 35, 36, 46, 49, 50).
SCD8562 Rev A Preliminary 12/07/09
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