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SSF5506 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 SSF5506
기능 N-Channel MOSFET
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SSF5506 데이터시트, 핀배열, 회로
Main Product Characteristics
VDSS
55V
RDS(on) 3.8mohm(typ.)
ID 140A
TO- 220
Features and Benefits
Advanced trench MOSFET process technology
Special designed for PWM, load switching and
general purpose applications
Ultra low on-resistance with low gate charge
Fast switching and reverse body recovery
175operating temperature
Lead free product
SSF5506
55V N-Channel MOSFET
Marking and Pin
Assignment
Schematic Diagram
Description
It utilizes the latest trench processing techniques to achieve the high cell density and reduces the
on-resistance with high repetitive avalanche rating. These features combine to make this design an extremely
efficient and reliable device for use in power switching application and a wide variety of other applications
Absolute Max Rating
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VDS
VGS
EAS
IAR
TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Drain-Source Voltage
Gate-to-Source Voltage
Single Pulse Avalanche Energy @ L=0.3mH
Avalanche Current @ L=0.3mH
Operating Junction and Storage Temperature Range
Max.
140
100
520
220
1.5
55
± 20
735
70
-55 to + 175
Units
A
W
W/°C
V
V
mJ
A
°C
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Page 1 of 7
Rev.1.0




SSF5506 pdf, 반도체, 판매, 대치품
Typical Electrical and Thermal Characteristics
SSF5506
55V N-Channel MOSFET
Figure 1: Typical Output Characteristics
Figure 2. Gate to source cut-off voltage
Figure 3. Drain-to-Source Breakdown Voltage vs.
Temperature
Figure 4: Normalized On-Resistance Vs. Case
Temperature
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Rev.1.0

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SSF5506 전자부품, 판매, 대치품
Ordering and Marking Information
SSF5506
55V N-Channel MOSFET
Device Marking: SSF5506
Package (Available)
TO-220
Operating Temperature Range
C : -55 to 175 ºC
Devices per Unit
Packag Units/Tu Tubes/Inner
e Type be
Box
TO220
50
20
Units/Inner
Box
1000
Inner
Boxes/Carton
Box
6
Units/Carton
Box
6000
Reliability Test Program
Test Item Conditions
High
Tj=125to 175@
Temperature 80% of Max
Reverse
VDSS/VCES/VR
Bias(HTRB)
High
Tj=150or 175@
Temperature 100% of Max VGSS
Gate
Bias(HTGB)
Duration
168 hours
500 hours
1000 hours
Sample Size
3 lots x 77 devices
168 hours 3 lots x 77 devices
500 hours
1000 hours
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SSF5506

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N-Channel MOSFET

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