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BU2152FS 데이터시트 PDF




ROHM Semiconductor에서 제조한 전자 부품 BU2152FS은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 BU2152FS 기능
기능 4-input Serial-in / Parallel-out Drivers
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BU2152FS 데이터시트, 핀배열, 회로
Datasheet
Serial-in / Parallel-out Driver Series
4-input Serial-in / Parallel-out Drivers
BU2152FS
Description
BU2152FS is a CMOS output driver. It incorporates a
built-in shift register and a latch circuit to turn on a
maximum of 24 output by a 4-wire interface, linked to a
microcontroller.
A CMOS output can provides maximum 25mA current.
Key Specifications
Power supply voltage range:
Output voltage:
Operating temperature range:
2.7V to 5.5V
0V to VDD
-25°C to +85°C
Features
Possible to drive LED directly
24bit parallel output
Package
SSOP-A32
W(Typ) x D(Typ) x H(Max)
13.60mm x 7.80mm x 2.01mm
Pin Configurations
VSS 1
CLK 2
VSS 3
DATA 4
P1 5
P2 6
P3 7
P4 8
P5 9
P6 10
P7 11
P8 12
P9 13
P10 14
P11 15
P12 16
(Top View)
32 VDD
31 CLB
30 STB
29 SO
28 P24
27 P23
26 P22
25 P21
24 P20
23 P19
22 P18
21 P17
20 P16
19 P15
18 P14
17 P13
SSOP-A32
SSOP-A32
Block Diagrams
DATA
CLK
STB
CLB
Controller
Shift
Register
SO
Latch
Write Buffer
24bit
P1P24
Product structureSilicon monolithic integrated circuit
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product has no designed protection against radioactive rays
1/12
TSZ02201-0RHR1GZ00150-1-2
24.Aug.2015 Rev.002




BU2152FS pdf, 반도체, 판매, 대치품
BU2152FS
Electrical Characteristics (Unless otherwise specified VDD=5V, VSS=0V, TA =25°C)
Parameter
Limits
Symbol
Symbol
Min Typ Min
Input High-level Voltage
Input Low-level Voltage
Output Hi-level Voltage
VIH 2.0
VIL -
VDD-1.5
VOH VDD-1.0
VDD-0.5
-
-
-
-
-
-
-
-
0.6
-
-
-
1.5
V
V
V
Output Low-level Voltage
VOL
Input High-level Leak Current
Input Low-level Leak Current
IIH
IIL
-
-
-
-
- 1.0
V
- 0.8
- 1 μA
- 1 μA
Quiescent Current
IDD - - 5 μA
0.1µF
VDD
Limits
-
-
IOH=-25mA
IOH=-15mA
IOH=-10mA
IOL=+25mA
IOL=+15mA
IOL=+10mA
VIL=VSS, VIH=VDD,
OUTPUT:OPEN
0.1µF
VDD
VSS
P.G.
VIH
VIL
VSS
Figure 1. Input High/Low Voltage Measurement Circuit
VSS
P.G.
24 SO
SW1
1
1
SW2
2
Figure 2. Output High/Low Voltage Measurement Circuit
Test condition
VOLSet all data Low. SW2=2, SW1=1to24,SO.
VOHSet all data High. SW2=1, SW1=1to24,SO.
IOH IOL
VSS
VSS VSS
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
4/12
TSZ02201-0RHR1GZ00150-1-2
24.Aug.2015 Rev.002

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BU2152FS 전자부품, 판매, 대치품
BU2152FS
Timing Chart
CLK
DATA
DATA24 DATA23 DATA22
DATA2 DATA1
STB
P1P24
SO
Previous
DATA
Previous Previous
DATA24 DATA23
DATA
Previous
DATA2
Previous
DATA1
DATA24
DATA23
DATA22
Figure 5. Timing Chart
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 24 data bits
into the DATA terminal.
2. P1 to P24 parallel output data of the shift register is set after the 24th clock by the LCK.
3. Since the STB is a level trigger latch, data is retained in the Hsection and renewed in the Lsection of the
STB.
4. The final stage data of the shift register is outputted to the SO by synchronizing with the rise time of the CLK.
Truth Table
Input
CLK STB
××
H
L
HL
CLB Function
L
All the data of the latch circuit are set to H(data of shift register does not
change), all the parallel outputs are H.
H
Serial data of DATA pin are latched to the shift register.
At this time, the data of the latch circuit does not change.
The data of the shift register are transferred to the latch circuit, and the data of
H the latch circuit are outputted from the parallel output pin.
The data of the shift register shifts 1bit, and the data of the latch circuit and
parallel output also change.
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
7/12
TSZ02201-0RHR1GZ00150-1-2
24.Aug.2015 Rev.002

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