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PDF MG84FL54B Data sheet ( Hoja de datos )
| Número de pieza | MG84FL54B | |
| Descripción | Full-Speed USB micro-controller | |
| Fabricantes | Megawin Technology | |
| Logotipo |  |
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MG84FL54B
Full-Speed USB micro-controller
Features
z 1-T 8051 CPU Core
z 16K bytes of on-chip Flash program memory with ISP/IAP function
z 256 bytes internal scratch-pad RAM and 576 bytes on-chip expanded RAM (XRAM)
z Dual DPTR (Data Pointer register)
z Four and half configurable I/O ports
z Three 16-bits Timers
z Enhanced UART
z Two-priority-level interrupt structure
z Four external interrupts, INT0, INT1, INT2 and INT3
z Keypad interrupt (P0)
z Wake-up from power-down mode and idle mode
z Serial Peripheral Interface (SPI)
z 2-wire Serial Interface (TWSI)
z One-time-enabled Watch-dog Timer (WDT)
z Programmable system clock
z USB specification 2.0 and 1.1 compliant
- Built in full speed (12Mbps) USB transceiver
- Intel 8X931 like USB control flow
- One 256 bytes FIFO for USB endpoint-shared buffer
¾ Maximum 64 bytes data for EP0 control-in/out buffer
¾ Maximum 64 bytes data for EP1 bulk/interrupt-in buffer
¾ Maximum 64 bytes data for EP2 bulk/interrupt/isochronous-in buffer, it could be configured to two 32
bytes dual-buffer-mode in bulk and isochronous operating.
¾ Maximum 64 bytes data for EP3 bulk/interrupt/isochronous-out buffer, it could be configured to two 32
bytes dual-buffer-mode in bulk and isochronous operating. Additionally, it also can be configured to an
interrupt-in buffer on EP3 function.
- Supports USB suspend/resume and remote wake-up event
- Firmware-controlled USB connection/disconnection mechanism
- Support USB DFU (Device Firmware Update)
z Power saving modes
- Idle mode
- Power-down mode
z Operating voltage
- 2.4 ~ 5.5V on VDD_IO, 2.7V ~ 3.6V on VDD_CORE and VDD_PLL, 3.0V~3.6V on VDDA.
z Operating temperature
- Industrial (-40°C to +85°C)*
z Maximum operating frequency
- Up to 25MHz, Industrial range
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product
without notice.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
2009/09. version A3
MEGAWIN
1 page  
17.2.4. Slave Receiver Mode ............................................................................................. 76
17.3. Miscellaneous States.............................................................................................77
17.4. Using the TWSI...................................................................................................... 78
17.5. Sample Code for TWSI..........................................................................................84
18. One-Time-Enabled Watchdog Timer (WDT)............................................... 85
18.1. WDT Block Diagram ..............................................................................................85
18.2. WDT During Idle and Power Down ........................................................................ 86
18.3. WDT Automatically Enabled by Hardware ............................................................. 86
18.4. WDT Overflow Period ............................................................................................86
18.5. Sample Code for WDT...........................................................................................86
19. Universal Serial Bus (USB)......................................................................... 88
19.1. USB Block Diagram ...............................................................................................88
19.2. USB FIFO Management ........................................................................................ 88
19.3. USB Interrupt .........................................................................................................89
19.4. USB Special Function Registers............................................................................ 89
19.4.1. USB SFR Memory Mapping ................................................................................... 90
19.4.2. USB SFR Description ............................................................................................. 91
20. ISP and IAP ................................................................................................ 99
20.1. Flash Memory Configuration.................................................................................. 99
20.2. In-System-Programming (ISP)............................................................................... 99
20.2.1. ISP/IAP Register..................................................................................................... 99
20.2.2. Description for ISP Operation............................................................................... 101
20.2.3. Sample Code for ISP............................................................................................ 102
20.3. In-Application-Programming (IAP) ....................................................................... 103
20.3.1. IAP-memory Boundary/Range.............................................................................. 103
20.3.2. Update data in IAP-memory ................................................................................. 103
21. Instruction Set ........................................................................................... 104
21.1. Arithmetic Operations .......................................................................................... 105
21.2. Logic Operations.................................................................................................. 106
21.3. Data Transfer.......................................................................................................107
21.4. Boolean Variable Manipulation ............................................................................ 108
21.5. Program and Machine Control ............................................................................. 109
22. Absolute Maximum Rating ........................................................................ 110
23. Electrical Characteristics........................................................................... 110
23.1. Global DC Electrical Characteristics .................................................................... 110
23.2. USB Transceiver Electrical Characteristics ......................................................... 111
24. Field Applications...................................................................................... 112
25. Order Information...................................................................................... 112
26. Package Dimension .................................................................................. 112
27. Revision History ........................................................................................ 113
MEGAWIN
MG84FL54B Data sheet
5
5 Page 
4. Hardware Option
The Hardware Option defines the device behavior which cannot be programmed or controlled by firmware. The
hardware options can only be programmed by a universal Writer/Programmer or Megawin proprietary Writer.
After whole-chip erased, all the hardware options are left in “disabled” state. The MG84FL54B has the following
Hardware Options:
ISP-memory Space:
The ISP-memory space is specified by its starting address. And, its higher boundary is limited by Flash end
address (See 20.1 Flash Memory Configuration). The following table shows ISP-memory size setting supplied
on MG84FL54B.
Table 4-1 ISP-memory Size
Item ISP-memory Size
1 4K bytes
2 3.5K bytes
3 3K bytes
4 2.5K bytes
5 2K bytes
6 1.5K bytes
7 1K bytes
8 (No ISP space is configured.)
ISP Start Address
0x3000
0x3200
0x3400
0x3600
0x3800
0x3A00
0x3C00
ISP Disabled
IAP-memory Space:
The IAP-memory space is specified by its low boundary. And, its higher boundary is limited by the starting
address of the ISP-memory space if the ISP-memory is configured; otherwise, its higher boundary is located at
address 0x3FFF (See 20.1 Flash Memory Configuration). The following table shows IAP-memory size setting
supplied on MG84FL54B.
Table 4-2 IAP-memory Size
IAP-memory Size
1 15.5K bytes
2 15K bytes
3 14.5K bytes
4 14K bytes
5 13.5K bytes
6 13K bytes
7 12.5K bytes
8 12K bytes
9 11.5K bytes
10 11K bytes
11 10.5K bytes
12 10K bytes
13 9.5K bytes
14 9K bytes
15 8.5K bytes
16 8K bytes
17 7.5K bytes
18 7K bytes
19 6.5K bytes
20 6K bytes
21 5.5K bytes
22 5K bytes
23 4.5K bytes
24 4K bytes
25 3.5K bytes
26 3K bytes
27 2.5K bytes
28 2K bytes
29 1.5K bytes
30 1K bytes
31 0.5K bytes
32 IAP Disabled
HWBS:
[enabled]: When power-up, CPU will boot from ISP-memory if ISP-memory is configured.
[disabled]: CPU always boots from AP-memory.
HWBS2:
MEGAWIN
MG84FL54B Data sheet
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