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부품번호 DA14583 기능
기능 Low Power Bluetooth Smart SoC
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DA14583 데이터시트, 핀배열, 회로
DATASHEET - TARGET
MARCH 06, 2015 V1.1
DA14583
Low Power Bluetooth Smart SoC with Flash memory
General description
Memories
The DA14583 integrated circuit has a fully integrated
radio transceiver and baseband processor for Blue-
tooth® Smart. It can be used as a standalone applica-
tion processor or as a data pump in hosted systems.
1 Mbit Flash memory
32 kB One-Time-Programmable (OTP) memory
42 kB System SRAM
84 kB ROM
8 kB Retention SRAM
The DA14583 supports a flexible memory architecture,
Power management
including 1 Mbit of Flash memory, for storing Bluetooth
Integrated Buck mode DC-DC converter
profiles and custom application code, which can be
Embedded charge pump for Flash programming
updated over the air (OTA). The qualified Bluetooth
P0, P1, and P2 ports with 3.3 V tolerance
Smart protocol stack is stored in a dedicated ROM. All
software runs on the ARM® Cortex®-M0 processor via
Supports coin (typ. 3.0 V) battery cells
10-bit ADC for battery voltage measurement
a simple scheduler.
Digital controlled oscillators
The Bluetooth Smart firmware includes the L2CAP ser-
vice layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT)
and the Generic Access Profile (GAP). All profiles pub-
lished by the Bluetooth SIG as well as custom profiles
are supported.
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
24 general purpose I/Os
2 UARTs with hardware flow control up to 1 MBd
The transceiver interfaces directly to the antenna and
SPI+™ interface
is fully compliant with the Bluetooth 4.1 standard.
I2C bus at 100 kHz, 400 kHz
The DA14583 has dedicated hardware for the Link
Layer implementation of Bluetooth Smart and interface
controllers for enhanced connectivity capabilities.
3-axes capable Quadrature Decoder
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Features
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
Complies with Bluetooth V4.1, ETSI EN 300 328 and
switching required
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
Supply current at VBAT3V:
(US) and ARIB STD-T66 (Japan)
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
Processing power
0 dBm transmit output power
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
-20 dBm output power in “Near Field Mode”
face -93 dBm receiver sensitivity
Dedicated Link Layer Processor
Packages:
AES-128 bit encryption Processor
QFN 40 pins, 5 mm x 5 mm
________________________________________________________________________________________________
System diagram
© 2014 Dialog Semiconductor
1 www.dialog-semiconductor.com




DA14583 pdf, 반도체, 판매, 대치품
2. Pinout
The DA14583 comes in a Quad Flat Package No
Leads (QFN) with 40 pins.
The pin/ball assignment is depicted in the following fig-
ure:
P0_0
P0_1
P0_2
P0_3
VCC_FLASH
P0_4
P0_5
P2_1
P0_6
P0_7
1
2
3
4
5
6
7
8
9
10
DA14583
(Top View)
30 XTAL16Mm
29 XTAL16Mp
28 P1_3
27 P1_2
26 SW_CLK
25 SWDIO
24 P1_1
23 VBAT1V
22 P1_0
21 SWITCH
Pin 0: GND
plane
Figure 2 QFN40 pin assignment
Table 1: Ordering information (samples)
Part number
DA14583 - 01F01AT1
Package
QFN40
Size (mm)
5x5
Shipment form
Tray
Pack quantity
50
Table 2: Ordering information (production)
Part number
DA14583 - 01F01AT2
Package
QFN40
Size (mm)
5x5
Shipment form
Reel
Pack quantity
5000
© 2014 Dialog Semiconductor 4 Target - March 06, 2015 v1.1

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DA14583 전자부품, 판매, 대치품
3. System overview
The DA14583 contains the following internal blocks:
3.1 ARM CORTEXM0 CPU
The Cortex-M0 processor is a 32-bit Reduced Instruc-
tion Set Computing (RISC) processor with a von Neu-
mann architecture (single bus interface). It uses an
instruction set called Thumb, which was first supported
in the ARM7TDMI processor; however, several newer
instructions from the ARMv6 architecture and a few
instructions from the Thumb-2 technology are also
included. Thumb-2 technology extended the previous
Thumb instruction set to allow all operations to be car-
ried out in one CPU state. The instruction set in
Thumb-2 includes both 16-bit and 32-bit instructions;
most instructions generated by the C compiler use the
16-bit instructions, and the 32-bit instructions are used
when the 16-bit version cannot carry out the required
operations. This results in high code density and
avoids the overhead of switching between two instruc-
tion sets.
In total, the Cortex-M0 processor supports only 56
base instructions, although some instructions can have
more than one form. Although the instruction set is
small, the Cortex-M0 processor is highly capable
because the Thumb instruction set is highly optimized.
Academically, the Cortex-M0 processor is classified as
load-store architecture, as it has separate instructions
for reading and writing to memory, and instructions for
arithmetic or logical operations that use registers.
Features
• Thumb instruction set. Highly efficient, high code
density and able to execute all Thumb instructions
from the ARM7TDMI processor.
• High performance. Up to 0.9 DMIPS/MHz (Dhrys-
tone 2.1) with fast multiplier.
• Built-in Nested Vectored Interrupt Controller (NVIC).
This makes interrupt configuration and coding of
exception handlers easy. When an interrupt request
is taken, the corresponding interrupt handler is exe-
cuted automatically without the need to determine
the exception vector in software.
• Interrupts can have four different programmable pri-
ority levels. The NVIC automatically handles nested
interrupts.
• The design is configured to respond to exceptions
(e.g. interrupts) as soon as possible (minimum 16
clock cycles).
• Non maskable interrupt (NMI) input for safety critical
systems.
• Easy to use and C friendly. There are only two
modes (Thread mode and Handler mode). The
whole application, including exception handlers, can
be written in C without any assembler.
• Built-in System Tick timer for OS support. A 24-bit
timer with a dedicated exception type is included in
the architecture, which the OS can use as a tick
timer or as a general timer in other applications with-
out an OS.
• SuperVisor Call (SVC) instruction with a dedicated
SVC exception and PendSV (Pendable SuperVisor
service) to support various operations in an embed-
ded OS.
• Architecturally defined sleep modes and instructions
to enter sleep. The sleep features allow power con-
sumption to be reduced dramatically. Defining sleep
modes as an architectural feature makes porting of
software easier because sleep is entered by a spe-
cific instruction rather than implementation defined
control registers.
• Fault handling exception to catch various sources of
errors in the system.
• Support for 24 interrupts.
• Little endian memory support.
• Wake up Interrupt Controller (WIC) to allow the pro-
cessor to be powered down during sleep, while still
allowing interrupt sources to wake up the system.
• Halt mode debug. Allows the processor activity to
stop completely so that register values can be
accessed and modified. No overhead in code size
and stack memory size.
• CoreSight technology. Allows memories and periph-
erals to be accessed from the debugger without halt-
ing the processor.
• Supports Serial Wire Debug (SWD) connections.
The serial wire debug protocol can handle the same
debug features as the JTAG, but it only requires two
wires and is already supported by a number of
debug solutions from various tools vendors.
• Four (4) hardware breakpoints and two (2) watch
points.
• Breakpoint instruction support for an unlimited num-
ber of software breakpoints.
• Programmer’s model similar to the ARM7TDMI pro-
cessor. Most existing Thumb code for the
ARM7TDMI processor can be reused. This also
makes it easy for ARM7TDMI users, as there is no
need to learn a new instruction set.
3.2 BLUETOOTH SMART
3.2.1 BLE Core
The BLE (Bluetooth Low Energy) core is a qualified
Bluetooth baseband controller compatible with the
Bluetooth Smart specification and it is in charge of
packet encoding/decoding and frame scheduling.
Note: Deep Sleep mode is not supported in DA14583.
Features
• All device classes support (Broadcaster, Central,
© 2014 Dialog Semiconductor 7 Target - March 06, 2015 v1.1

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