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부품번호 AP0101CS 기능
기능 High-Dynamic Range (HDR) Image Signal Processor
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AP0101CS 데이터시트, 핀배열, 회로
AP0101CS HDR: Image Signal Processor (ISP)
Features
AP0101CS High-Dynamic Range (HDR)
Image Signal Processor (ISP)
AP0101CS Datasheet, Rev. 7
For the latest product datasheet, please visit www.onsemi.com
Features
• Supports ON Semiconductor sensors with up to
1.2 Mp (1280x960)
• 45 fps at 1.2 Mp, 60 fps at 720p
• Optimized for operation with HDR sensors
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz flicker
avoidance
• Adaptive Local Tone Mapping (ALTM)
• Test Pattern Generator
• Two-wire serial programming interface
• Interface to low-cost Flash or EPROM through SPI
bus (to configure and load patches)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Dual Band IR filter support
Applications
• SMPTE296 HDCCTV cameras
• Surveillance network IP cameras
Table 1:
Key Performance Parameters
Parameter
Value
Primary camera
interface
Parallel
Primary camera input
format
Output interface
RAW12 Linear/Companded Bayer
data
Up to 20-bit Parallel1
Output format
YUV422 8-bit,10-bit, and
SMPTE296M
10-, 12-bit tone-mapped Bayer
Maximum resolution 1280x960 (1.2 Mp)
Input clock range2
6-30 MHz
Maximum frame rate3 45 fps at 1.2 Mp, 60 fps at 720p
Maximum output clock
frequency
Parallel clock up to 84 MHz
VDDIO_S 1.8 or 2.8 V nominal
Supply VDDIO_H
voltage VDD_REG
2.5 or 3.3 V nominal
1.8V nominal
VDDIO_OTPM 2.5 or 3.3 V nominal
Operating temperature
(ambient - TA)
–30°C to +70°C
Typical power
consumption4
130 mW
Notes: 1. 20-bit in one pixel clock format is only available in
SMPTE mode with the use of 4 GPIOs.
2. With input clock below 10 MHz, the two wire
serial interface is supported only up to 100 KHz
3. Maximum frame rate depends on output inter-
face and data format configuration used.
4. 720p HDR 60 fps 74.25 MHz YCbCr_422_16
AP0101CS/D Rev. 7, 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,




AP0101CS pdf, 반도체, 판매, 대치품
AP0101CS HDR: Image Signal Processor (ISP)
General Description
General Description
The ON Semiconductor AP0101CS is a high-performance, ultra-low power in-line,
digital image processor optimized for use with High Dynamic Range (HDR) sensors. The
AP0101CS provides full auto-functions support (AWB and AE) and Adaptive Local Tone
Mapping (ALTM) to enhance HDR images and advanced noise reduction which enables
excellent low-light performance.
Functional Overview
Figure 1 shows the typical configuration of the AP0101CS in a camera system. On the
host side, a two-wire serial interface is used to control the operation of the AP0101CS,
and image data is transferred using the parallel bus between the AP0101CS and the host.
The AP0101CS interface to the sensor also uses a parallel interface.
Figure 1: AP0101CS Connectivity
1.2Mp HDR Sensor
12-bit parallel
Two-wire serial I/F (Master)
Up to 20-bit parallel
Host
Two-wire serial IF (Slave)
System Interfaces
Figure 2 on page 5 shows typical AP0101CS device connections.
All power supply rails must be decoupled from ground using capacitors as close as
possible to the package.
The AP0101CS signals to the sensor and host interfaces can be at different supply voltage
levels to optimize power consumption and maximize flexibility. Table 4 on page 7
provides the signal descriptions for the AP0101CS.
AP0101CS/D Rev. 7, 1/16 EN
4 ©Semiconductor Components Industries, LLC,2016.

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AP0101CS 전자부품, 판매, 대치품
AP0101CS HDR: Image Signal Processor (ISP)
System Interfaces
Crystal Usage
As an alternative to using an external oscillator, a crystal may be connected between
EXTCLK and XTAL. Two small loading capacitors and a feedback resistor should be
added, as shown in Figure 3.
Figure 3: Using a Crystal Instead of an External Oscillator
AP0101
C1
EXTCLK
Rf=1MΩ
XTAL
C2
Rf represents the feedback resistor, an Rf value of 1Mwould be sufficient for AP0101CS.
C1 and C2 are decided according to the crystal or resonator CL specification. In the
steady state of oscillation, CL is defined as (C1 x C2)/(C1+C2). In fact, the I/O ports, the
bond pad, package pin and PCB traces all contribute the parasitic capacitance to C1 and
C2. Therefore, CL can be rewritten to be (C1* x C2*)/(C1*+C2*), where C1*=(C1+Cin,
stray) and C2*=(C2+Cout, stray). The stray capacitance for the IO ports, bond pad and
package pin are known which means the formulas can be rewritten as
C1*=(C1+1.5pF+Cin, PCB) and C2*=(C2+1.3pF+Cout, PCB).
Table 4: Pin Descriptions
Name
EXTCLK
Type
Input
XTAL
Output
RESET_BAR
SCLK
SDATA
SADDR
Input/PU
Input
I/O
Input
FRAME_SYNC
Input
STANDBY
SPI_SCLK
Input
Output
Description
Master input clock. This can either be a square-wave generated from an oscillator (in
which case the XTAL input must be left unconnected) or direct connection to a crystal.
If EXTCLK is connected to one pin of a crystal, the other pin of the crystal is connected to
XTAL pin; otherwise this signal must be left unconnected.
Master reset signal, active LOW. This signal has an internal pull up.
Two-wire serial interface clock (host interface).
Two-wire serial interface data (host interface).
Selects device address for the two-wire slave serial interface. When connected to GND
the device ID is 0x90. When wired to VDDIO_H, a device ID of 0xBA is selected.
This input can be used to set the output timing of the AP0101CS. This signal should be
connected to GND if not used.
Standby mode control, active HIGH.
Clock output for interfacing to an external SPI flash or EEPROM memory.
AP0101CS/D Rev. 7, 1/16 EN
7 ©Semiconductor Components Industries, LLC,2016.

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부품번호상세설명 및 기능제조사
AP0101CS

High-Dynamic Range (HDR) Image Signal Processor

ON Semiconductor
ON Semiconductor

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