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PDF SC9256 Data sheet ( Hoja de datos )
| Número de pieza | SC9256 | |
| Descripción | PLL FOR DIGITAL TUNING SYSTEM | |
| Fabricantes | Silan Semiconductors | |
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SC9256
PLL FOR DIGITAL TUNING SYSTEM
DESCRIPTION
The SC9256 is phase-locked loop (PLL) LSIs for digital tuning
systems (DTS) with built in 2 modulus prescalers.
All functions ate controlled through 3 serial bus lines. These LSIs are
used to configure high-performance digital tuning system.
DIP-16-300-2.54
FEATURES
* Optimal for configuring digital tuning systems in high-fi tuners and
car stereos.
* Built-in prescalers. Operate at input frequency ranging from 30~150
MHz during FMIN input (with 2 modulus prescaler) and at
0.5~40MHz during AMIN input (with 2 modulus prescaler or direct
dividing).
* 16 bit programmable counter, dual parallel output phase
comparator, crystal oscillator and reference counter.
* 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be
used.
* 15 possible reference frequencies. ( When using 4.5MHz crystal)
* Built-in 20 bit general-purpose counter for such uses as measuring
intermediate frequencies (IFIN1 and IFIN2)
* High-precision (±0.55~±7.15µs) PLL phase error detection.
* Numerous general-purpose I/O pins for such uses as peripheral
circuit control.
* All functions controlled through 3 serial bus lines.
*CMOS structure with operating power supply range of
VDD=5.0±0.5V.
SOP-16-300-1.27
* 3 N-channel open-drain output
ports (OFF withstanding voltage:
12V) for such uses as control
signal output.
* Standby mode function (turns off
FM, AM and IF amps) to save
current consumption.
ORDERING INFORMATION
Device
SC9256
SC9256S
Package
DIP-16-300-2.54
SOP-16-300-1.27
BLOCK DIAGRAM
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 1 of 22
1 page  
SC9256
FUNCTION DESCRIPTION
Serial I/O ports
As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the
2 sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the
controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8
address bits and 24 data bits.
Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit
address and functions of each register.
These registers consist of 24 bits and are selected by an 8 bit address.
A list of the address assignment for each register is given below under register assignments.
Register
Address
Contents of 24 bits
No. of bit
PLL divisor setting
16
Input
register 1
D0H
Reference frequency setting
PLL input and mode setting
Crystal oscillator selection
4
2
2
total 24
General=purpose counter control (including lock detection bit
4
control)
I/O port and general-purpose counter switching bits
3
I/O-5/CLK pin switching bit
1
Input
register 2
D2H
DO pin control
Test bit
1
1
I/O port control (also used as general-purpose counter input
5
selection bits)
Output data
9
total 24
Output
register 1
D1H
General-purpose counter numeric data
Not used
22
2
total 24
Lock detection data
5
I/O port control data
5
Output
register 2
D3H
Output data
Input data (undefined during output port selection)
4
5
Not used
5
total 24
When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is
performed.
When the CLOCK signal falls for 9 times, the output data are latched in parallel in the output registers. The
data are subsequently output serially from the data pin.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 5 of 22
5 Page 
SC9256
(3) Bits M5 sets the state for pin I/O-5/IFIN1; M6, for pin I/O-6/IFIN2.
These operations are valid when bits SC, IF1 and IF2 are all set to 1.
Address D2H
LSB
M5 M6
MSB
M5 M6
00
(*) 1
10
00
PIN STATES (When bits sc, IF1 and IF2 are all set to "1")
IFIN1
IFIN2
INPUT pulled down
INPUT pulled down
INPUT enabled
INPUT enabled
INPUT pulled down
INPUT pulled down
Note: Bits marked with an asterisk “(*)”are don’t care
(4) Bits f0~f9… The general-purpose counter results can be read in binary from bits f0~f9 of the output register
(D1H).
Address D1H
LSB MSB
f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 OVER BUSY "0" "0"
20 219
General-purpose counter data
(5) OVER and BUSY bits… Detect the operating state of the general-purpose counter.
Address D1H
MSB
OVER BUSY "0" "0"
BIT DATA = "1"
BIT DATA = "0"
General-purpose counter
option monitor bit
General-purpose counter
overflow detection bit
General-purpose counter
busy
Counted value in general-
purpose counter 220
(Overflow state)
General-purpose counter
ended counting
Counted value in general-
purpose counter 220 -1
Note: When using the general-purpose counter, before referring to the contents of the general-purpose counter
result bit (f0~f9), confirm that the busy bit is “0”(counting is ended) and the OVER bit is “0”(general-
purpose counter data are normal).
(6) START bit… When the data are set to “1”, the general-purpose counter is reset then counting begins.
Address D2H
LSB
start
MSB
0 Counting continues uninterrupted.
1 Counting begins after general - purpose counter is reset.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet SC9256.PDF ] | |
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