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PDF AS4C16M16D1A Data sheet ( Hoja de datos )
| Número de pieza | AS4C16M16D1A | |
| Descripción | 16M x 16 DDR1 | |
| Fabricantes | Alliance Semiconductor | |
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16Mx16 DDR1-AS4C16M16D1A
Revision History
AS4C16M16D1A - 66-pin TSOPII PACKAGE
Revision Details
Rev 1.1 Preliminary datasheet
Date
July 2015
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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16Mx16 DDR1-AS4C16M16D1A
P in Descriptions
Table 2. Pin Details
Symbol Type
Description
CK, CK
Input
Differential Clock: CK, CK are driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. Both CK and CK increment the internal
burst counter and controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
BA0, BA1
Input Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A12
Input
Address Inputs: A0-A12 are sampled during the BankActivate command (row
address A0-A12) and Read/Write command (column address A0-A8 with A10 defining
Auto Precharge).
CS Input Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS is sampled HIGH. CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
RAS
Input
Row Address Strobe: The RAS signal defines the operation commands in
conjunction with the CAS and WE signals and is latched at the positive edges of
CK. When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either
the BankActivate command or the Precharge command is selected by the WE
signal. When the WE is asserted "HIGH," the BankActivate command is selected and
the bank designated by BA is turned on to the active state. When the WE is asserted
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
CAS
Input
Column Address Strobe: The CAS signal defines the operation commands in
conjunction with the RAS and WE signals and is latched at the positive edges of
CK. When RAS is held "HIGH" and CS is asserted "LOW," the column access is
started by asserting CAS "LOW." Then, the Read or Write command is selected by
asserting WE "HIGH" or “LOW”.
WE Input Write Enable: The WE signal defines the operation commands in conjunction with
the RAS and CAS signals and is latched at the positive edges of CK. The WE input
is used to select the BankActivate or Precharge command and Read or Write
command.
LDQS,
UDQS
Input / Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data
Output
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
LDM,
UDM
DQ0 - DQ15
Input
Input /
Output
Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and
negative edges of LDQS and UDQS. The I/Os are byte-maskable during Writes.
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16Mx16 DDR1-AS4C16M16D1A
E xtended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE .
The state of A0 ~ A12, BA0 and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and
WE going low. (the device should have all banks idle with no bursts in progress prior to writing into the mode
register, and CKE should be High). A1 is used for setting driver strength to normal, or weak. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for
specific codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
01
RFU must be set to “0”
DS1 RFU must be set to “0” DS0 DLL Extended Mode Register
BA0 Mode
0 MRS
1 EMRS
A6 A1 Drive Strength
Comment
00
Full
01
Weak
10
RFU
Reserved For Future
1 1 Matched impedance Output driver matches impedance
A0 DLL
0 Enable
1 Disable
Confidential
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Rev.1.1 July 2015
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS4C16M16D1A.PDF ] | |
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