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PDF BR93G46-3B Data sheet ( Hoja de datos )
| Número de pieza | BR93G46-3B | |
| Descripción | MicroWire BUS EEPROM | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
Serial EEPROM series Standard EEPROM
MicroWire BUS EEPROM (3-Wire)
BR93G46-3B
●General Description
BR93G46-3B is serial EEPROM of serial 3-line Interface method.
They are 16bit organization and CS PIN is the third PIN in their PIN configuration.
●Features
■ 3-line communications of chip select, serial clock,
serial data input / output (the case where input and
output are shared)
■ Operations available at high speed 3MHz clock
(4.5V ~ 5.5V)
■ High speed write available (write time 5ms max.）
■ Same package and pin configuration from 1Kbit to
16Kbit
■ 1.7~5.5V single power source operation
■ Address auto increment function at read operation
■ Write mistake prevention function
» Write prohibition at power on
» Write prohibition by command code
» Write mistake prevention function at low voltage
■ Self-timed programming cycle
■ Program condition display by READY / BUSY
■ Compact package
SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/
TSSOP-B8J/DIP-T8/VSON008X2030
■ More than 40 years data retention
■ More than 1 million write cycles
■ Initial delivery state all addresses FFFFh
●Packages W(Typ.) x D(Typ.)x H(Max.)
DIP-T8
9.30mm x 6.50mm x 7.10mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
SOP8
5.00mm x 6.20mm x 1.71mm
TSSOP-B8J
3.00mm x 4.90mm x 1.10mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
MSOP8
2.90mm x 4.00mm x 0.90mm
SSOP-B8
3.00mm x 6.40mm x 1.35mm
VSON008X2030
2.00mm x 3.00mm x 0.60mm
●BR93G46-3B
Capacity Bit format
1Kbit
64×16
Type
Power source
voltage
DIP-T8*1
SOP8
SOP-J8
SSOP-B8 TSSOP-B8 TSSOP-B8J
MSOP8
VSON008
X2030
BR93G46-3B 1.7~5.5V
●●
●
●
●
● ●●
*1 DIP-T8 is not halogen free package
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product is not designed protection against radioactive rays
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BR93G46-3B
●Serial input / output timing
Datasheet
CS
tCSS
SK
tDIS
DI
DO(READ)
DO(WRITE)
tSV
tSKH
1/ fSK
tSKL
tD IH
tPD0
tPD1
STATUS VALID
tCSH
t DF
Figure 1. Sync data input / output timing
○Data is taken by DI sync with the rise of SK.
○At read operation, data is output from DO in sync with the rise of SK.
○The STATUS signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area
DO where CS is high, and valid until the next command start bit is input. And, while CS is low, DO becomes High-Z.
○After completion of each mode execution, set CS low once for internal circuit reset, and execute the following operation
mode.
○1/fSK is the SK clock cycle, even if fSK is maximum, the SK clock cycle can’t be tSKH(Min.)+tSKL(Min.)
○For “Write cycle time tE/W”, please see Figure 36,37,39,40.
○For “CS low time tCS”, please see Figure 36,37,39,40.
●Block diagram
CS Command decode
Control
SK
Clock generation
DI Command
register
DO Dummy bit
Power source voltage detection
Write
prohibition
Address
buffer
6bit
Data
register
16bit
High voltage occurrence
Address
decoder
R/W
amplifier
6bit
16bit
1,024 bit
EEPROM
Figure 2. Block diagram
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
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TSZ02201-09190G100150-1-2
18.FEB.2013 REV.001
5 Page 
BR93G46-3B
●Typical Performance Curves‐Continued
Datasheet
2.5
SPEC
2
1.5 Ta=-40℃
Ta= 25℃
Ta= 85℃
1
0.5
0
0 12 34 56
SUPPLY VOLTAGE: VCC(V)
Figure 20. Standby current
ISB1(CS=0V)
1000
100
Ta=-40℃
Ta= 25℃
Ta= 85℃
10
SPEC
SPEC
SPEC
1
0.1
0.01
0
12 34 5
SUPPLY VOLTAGE: VCC(V)
Figure 21. SK frequency fSK
6
500
400 Ta=-40℃
Ta= 25℃
Ta= 85℃
300
SPEC
SPEC
200
100
SPEC
0
0 12 3 45 6
SUPPLY VOLTAGE: VCC(V)
Figure 22. SK high time tSKH
500
400 Ta=-40℃
Ta= 25℃
Ta= 85℃
300
SPEC
200 SPEC
100
SPEC
0
0 12 3 45 6
SUPPLY VOLTAGE: VCC(V)
Figure 23. SK low time tSKL
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
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11 Page | ||
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| PDF Descargar | [ Datasheet BR93G46-3B.PDF ] | |
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