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PDF DP7419 Data sheet ( Hoja de datos )
| Número de pieza | DP7419 | |
| Descripción | Dual Digital Potentiometers | |
| Fabricantes | COPAL ELECTRONICS | |
| Logotipo |  |
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DP7419
Dual Digital Potentiometers (DP)
with 64 Taps and 2-wire Interface
FEATURES
Two linear-taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5k, 10k, 50k or
100k
Potentiometer control and memory access via
2-wire Interface (I2C like)
Low wiper resistance, typically 80
Four non-volatile wiper settings for each
potentiometer
Recall of wiper settings at power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Write protection for data register
DESCRIPTION
The DP7419 is two Digital Potentiometers (DPs)
integrated with control logic and 16 bytes of
NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DP.
Associated with each wiper control register are four 6-
bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data regis-
ters is via a 2-wire serial bus (I2C-like). On power-up,
the contents of the first data register (DR0) for each of
the two potentiometers is automatically loaded into its
respective wiper control registers (WCR).
The Write Protection (¯W¯P¯) pin protects against
inadvertent programming of the data register.
The DP7419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC (W)
(top view)
VCC 1
24 NC
RL0 2
23 NC
RH0 3
22 NC
RW0 4
21 NC
A2 5
20 A0
¯W¯P¯ 6 CAT 19 NC
SDA 7 5419 18 A3
A1 8
17 SCL
RL1 9
16 NC
RH1 10
15 NC
RW1 11
14 NC
GND 12
13 NC
TSSOP (Y)
(top view)
SDA 1
24 ¯W¯P¯
A1 2
23 A2
RL1 3
22 RW0
RH1 4
21 RH0
RW1 5
20 RL0
GND 6 CAT 19 VCC
NC 7 5419 18 NC
NC 8
17 NC
NC 9
16 NC
NC 10
15 NC
SCL 11
14 A0
A3 12
13 NC
For Ordering Information details, see page 15.
FUNCTIONAL DIAGRAM
RH0 RH1
SCL
SDA
WP
A0
A1
A2
A3
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
RW0
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RW1
RL0 RL1
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2115 Rev. H
1 page  
DP7419
WRITE CYCLES LIMITS
Symbol Parameter
Max Units
tWR Write Cycle Time
5 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Reference Test Method
Min Typ
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(2)
Endurance
Data Retention
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
2000
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Max
Units
Cycles/Byte
Years
Volts
mA
Figure 1. Bus Timing
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
STOP BIT
5 Doc. No. MD-2115 Rev. H
5 Page 
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
SCL
SDA
Voltage Out
RW
tWRID
DP7419
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 0 0 1 0 0 0 P0 C 7 6 5 4 3 2 1 0 C T
A
K
K00
KO
RP
T
Write Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 0 1 0 0 0 0 P0 C 7 6 5 4 3 2 1 0 C T
A
K
K00
KO
RP
T
Read Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 0 1 1 R1 R0 0 P0 C 7 6 5 4 3 2 1 0 C T
A
K
K00
KO
RP
T
Write Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 1 0 0 R1 R0 0 P0 C 7 6 5 4 3 2 1 0 C T
A
K
K00
KO
RP
T
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2115 Rev. H
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DP7419.PDF ] | |
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