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DP7241 데이터시트 PDF




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광범위하게 사용되는 반도체 소자입니다.


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부품번호 DP7241 기능
기능 Quad Digital Potentiometer
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DP7241 데이터시트, 핀배열, 회로
Quad Digital Potentiometer (DP) with
64 Taps and 2-wire Interface
DP7241
FEATURES
Four linear-taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kŸ, 10kŸ, 50kŸ or
100kŸ
Potentiometer control and memory access via
2-wire interface (I2C like)
Low wiper resistance, typically 80W
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
20-lead SOIC and TSSOP packages
Industrial temperature range
For Ordering Information details, see page 15.
DESCRIPTION
The DP7241 is four Digital Potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of 63 resistive elements connected between
two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
serial bus (I2C-like). On power-up, the contents of the
first data register (DR0) for each of the four
potentiometers is automatically loaded into its
respective wiper control register (WCR).
The DP7241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC 20 Lead (W)
TSSOP 20 Lead (Y)
RW0 1
20 VCC
RL0 2
19 RW3
RH0 3
18 RL3
A0 4
17 RH3
A2 5 CAT 16 A1
RW1 6 5241 15 A3
RL1 7
14 SCL
RH1 8
13 RW2
SDA 9
12 RL2
GND 10
11 RH2
SCL
SDA
A0
A1
A2
A3
FUNCTIONAL DIAGRAM
2-WIRE BUS
INTERFACE
CONTROL
LOGIC
RH0 RH1 RH2 RH3
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
RW0
RW1
RW2
RW3
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2011 Rev. P




DP7241 pdf, 반도체, 판매, 대치품
DP7241
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Test Conditions
Min Typ Max Units
ICC Power Supply Current
fSCL = 400kHz
1 mA
ISB Standby Current (VCC = 5.0V)
VIN = GND or VCC;
SDA = GND; RWX = GND (2)
1 µA
ILI Input Leakage Current
VIN = GND to VCC
10 µA
ILO Output Leakage Current
VOUT = GND to VCC
10 µA
VIL Input Low Voltage
-1 VCC x 0.3 V
VIH Input High Voltage
VCC x 0.7
VCC + 1.0 V
VOL1 Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
0.4 V
CAPACITANCE
TA = 25°C, f = 1.0MHz, VCC = 5V
Symbol Parameter
Test Conditions Min Typ Max Units
CI/O(1)
CIN(1)
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL)
VI/O = 0V
VIN = 0V
8 pF
6 pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
fSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (For a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Min
1.2
0.6
1.2
0.6
0.6
0
100
0.6
50
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) All four wiper terminals RW0, RW1, RW2, and RW3 are tied to ground.
Typ Max Units
400 kHz
50 ns
0.9 µs
µs
µs
µs
µs
µs
ns
ns
0.3 µs
300 ns
µs
ns
Typ Max Units
1 ms
1 ms
Doc. No. MD-2011 Rev. P
4 © NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice

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DP7241 전자부품, 판매, 대치품
WRITE OPERATION
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of DP7241. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The DP7241
acknowledges once more and the Master generates
the STOP condition, at which time if a non-volatile
data register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
DP7241
Acknowledge Polling
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the DP7241 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the DP7241 is still
busy with the write operation, no ACK will be returned.
If the DP7241 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
Figure 5. Slave Address Bits
DP7241 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE/DP
ADDRESS
Fixed
Variable
INSTRUCTION
BYTE
DR WCR DATAop code
Pot/WCR Data Register
Address Address
S
T
O
P
SDA LINE S
P
A AA
C CC
K KK
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
7
Doc. No. MD-2011 Rev. P

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관련 데이터시트

부품번호상세설명 및 기능제조사
DP7241

Quad Digital Potentiometer

COPAL ELECTRONICS
COPAL ELECTRONICS

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