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DP7259 데이터시트 PDF




COPAL ELECTRONICS에서 제조한 전자 부품 DP7259은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 DP7259 자료 제공

부품번호 DP7259 기능
기능 Quad Digital Potentiometer
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DP7259 데이터시트, 핀배열, 회로
Quad Digital Potentiometers
(DP) with 256 Taps and 2-wire Interface
DP7259
FEATURES
Four linear taper digital potentiometers
256 resistor taps per potentiometer
End to end resistance 50kŸ or 100kŸ
Potentiometer control and memory access via
2-wire interface (I2C like)
Low wiper resistance, typically 100Ÿ
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP packages
Industrial temperature range
For Ordering Information details, see page 15.
DESCRIPTION
The DP7259 is four digital potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
serial bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers
is automatically loaded into its respective wiper
control registers.
The DP7259 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40ºC to 85ºC
industrial operating temperature ranges and offered in
a 24-lead SOIC and TSSOP package.
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
NC 1
A0 2
RW3
RH3
RL3
3
4
5
NC 6
VCC 7
RLO 8
RHO 9
RWO 10
A2 11
¯W¯P¯ 12
24 A3
23 SCL
22 RL2
21 RH2
20 RW2
19 NC
18 GND
17 RW1
16 RH1
15 RL1
14 A1
13 SDA
FUNCTIONAL DIAGRAM
SCL
SDA
WP
A0
A1
A2
A3
RH0
RH1
RH2
RH3
2-WIRE BUS
INTERFACE
WIPER CONTROL
REGISTERS
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
RW0
RW1
RW2
RW3
RL0 RL1 RL2
RL3
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2000 Rev. H




DP7259 pdf, 반도체, 판매, 대치품
DP7259
D.C. OPERATING CHARACTERISTICS
VCC = +2.5V to +6.0V, unless otherwise specified.
Symbol Parameter
Test Conditions
ICC1 Power Supply Current
ICC2
Power Supply Current
Non-volatile WRITE
fSCL = 400kHz, SDA = Open
VCC = 6V, Inputs = GND
fSCK = 400kHz, SDA Open
VCC = 6V, Input = GND
ISB Standby Current (VCC = 5.0V) VIN = GND or VCC, SDA = Open
ILI Input Leakage Current
VIN = GND to VCC
ILO Output Leakage Current
VOUT = GND to VCC
VIL Input Low Voltage
VIH Input High Voltage
VOL1 Output Low Voltage (VCC = 3.0V) IOL = 3 mA
Min
-1
VCC x 0.7
Max
1
5
5
10
10
VCC x 0.3
VCC + 1.0
0.4
Capacitance
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
CI/O(1)
CIN(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, ¯W¯P¯)
Conditions
VI/O = 0V
VIN = 0V
Max.
8
6
A.C. CHARACTERISTICS
Symbol Parameter
2.5V - 6.0V
Min.
Max.
fSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
mA
mA
µA
µA
µA
V
V
V
Units
pF
pF
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2000 Rev. H
4 © NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice

4페이지










DP7259 전자부품, 판매, 대치품
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Condition
DP7259
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
SDA
SCL
START CONDITION
STOP CONDITION
Figure 4. Acknowledge Condition
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Slave Address Bits
ACKNOWLEDGE
DP7259 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
7
Doc. No. MD-2000 Rev. H

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