Datasheet.kr   

KAI-16050 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 KAI-16050은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 KAI-16050 자료 제공

부품번호 KAI-16050 기능
기능 Interline CCD Image Sensor
제조업체 ON Semiconductor
로고 ON Semiconductor 로고


KAI-16050 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

KAI-16050 데이터시트, 핀배열, 회로
KAI-16050
4896 (H) x 3264 (V)
Interline CCD Image Sensor
Description
The KAI16050 Image Sensor is a 16megapixel CCD in an
APSH optical format. Based on the TRUESENSE 5.5 micron
Interline Transfer CCD Platform, the sensor features broad dynamic
range, excellent imaging performance, and a flexible readout
architecture that enables use of 1, 2, or 4 outputs for full resolution
readout up to 8 frames per second. A vertical overflow drain structure
suppresses image blooming and enables electronic shuttering for
precise exposure control.
The sensor is available with the TRUESENSE Sparse Color Filter
Pattern, a technology which provides a 2x improvement in light
sensitivity compared to a standard color Bayer part.
The sensor shares common PGA pinout and electrical
configurations with other devices based on the TRUESENSE
5.5 micron Interline Transfer CCD Platform, allowing a single camera
design to be leveraged to support multiple members of this sensor
family.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Interline CCD; Progressive Scan
Total Number of Pixels
4964 (H) x 3332 (V)
Number of Effective Pixels
4920 (H) x 3288 (V)
Number of Active Pixels
4896 (H) x 3264 (V)
Pixel Size
5.5 mm (H) x 5.5 mm (V)
Active Image Size
26.93 mm (H) x 17.95 mm (V)
32.36 mm (diag.) APSH Format
Aspect Ratio
Number of Outputs
Charge Capacity
Output Sensitivity
Quantum Efficiency
Pan (AXA, QXA, PXA)
R, G, B (FXA, QXA)
R, G, B (CXA, PXA)
Read Noise (f = 40 MHz)
Dark Current
Photodiode
VCCD
Dark Current Doubling Temp.
Photodiode
VCCD
Dynamic Range
Charge Transfer Efficiency
Blooming Suppression
Smear
Image Lag
Maximum Pixel Clock Speed
Maximum Frame Rates
Quad Output
Dual Output
Single Output
Package
Cover Glass
3:2
1, 2, or 4
20,000 electrons
34 mV/e
43%
28%, 35%, 38%
29%, 35%, 37%
12 electrons rms
2 electrons/s
140 electrons/s
7°C
9°C
64 dB
0.999999
> 300 X
Estimated 100 dB
< 10 electrons
40 MHz
8 fps
4 fps
2 fps
72 pin PGA
AR coated, 2 Sides
NOTE: All parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
August, 2015 Rev. 7
1
www.onsemi.com
Figure 1. KAI16050 CCD Image Sensor
Features
Bayer Color Pattern, TRUESENSE Sparse
Color Filter Pattern, and Monochrome
Configurations
Progressive Scan Readout
Flexible Readout Architecture
High Frame Rate
High Sensitivity
Low Noise Architecture
Excellent Smear Performance
Package Pin Reserved for Device
Identification
Applications
Industrial Imaging and Inspection
Traffic
Security
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Publication Order Number:
KAI16050/D




KAI-16050 pdf, 반도체, 판매, 대치품
DEVICE DESCRIPTION
Architecture
KAI16050
RDc
Rc
VDDc
VOUTc
1 10 22 182
2448
2448
182 22 10 1
GND
OGc
ÉÉÉÉÉÉÉÉÉÉÉF2L2DÉÉÉÉÉÉÉÉÉÉÉ
H2SLc
12
RDd
Rd
VDDd
VOUTd
GND
OGd
H2SLd
V1T V1T
V2T V2T
V3T V3T
V4T V4T
DevID
ESD 22 12
4896H x 3264V
5.5 mm x 5.5 mm Pixels
12 22
ESD
V1B V1B
V2B V2B
V3B V3B
V4B V4B
12 Buffer
RDa
Ra
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉVDDa
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉVOUTa
1 10 22 182
2448
22 Dark
FLD (Last VCCD Phase = V1 H1S)
2448
182 22 10 1
RDb
Rb
VDDb
VOUTb
GND
OGa
H2SLa
GND
OGb
H2SLb
Figure 2. Block Diagram
Dark Reference Pixels
There are 22 dark reference rows at the top and 22 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
Active Buffer Pixels
12 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
These pixels are light sensitive but are not tested for defects
and nonuniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electronhole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and nonlinearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
www.onsemi.com
4

4페이지










KAI-16050 전자부품, 판매, 대치품
KAI16050
Table 5. PIN DESCRIPTION
Pin Name
Description
1 V3B Vertical CCD Clock, Phase 3, Bottom
3 V1B Vertical CCD Clock, Phase 1, Bottom
4 V4B Vertical CCD Clock, Phase 4, Bottom
5
VDDa
Output Amplifier Supply, Quadrant a
6 V2B Vertical CCD Clock, Phase 2, Bottom
7
GND
Ground
8 VOUTa Video Output, Quadrant a
9 Ra Reset Gate, Quadrant a
10 RDa Reset Drain, Quadrant a
11 H2SLa Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant a
12 OGa Output Gate, Quadrant a
13 H1Ba Horizontal CCD Clock, Phase 1, Barrier,
Quadrant a
14 H2Ba Horizontal CCD Clock, Phase 2, Barrier,
Quadrant a
15 H2Sa Horizontal CCD Clock, Phase 2,
Storage, Quadrant a
16 H1Sa Horizontal CCD Clock, Phase 1,
Storage, Quadrant a
17 SUB Substrate
18 FDGab Fast Line Dump Gate, Bottom
19 N/C No Connect
20 FDGab Fast Line Dump Gate, Bottom
21 H2Sb Horizontal CCD Clock, Phase 2,
Storage, Quadrant b
22 H1Sb Horizontal CCD Clock, Phase 1,
Storage, Quadrant b
23 H1Bb Horizontal CCD Clock, Phase 1, Barrier,
Quadrant b
24 H2Bb Horizontal CCD Clock, Phase 2, Barrier,
Quadrant b
25 H2SLb Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant b
26 OGb Output Gate, Quadrant b
27 Rb Reset Gate, Quadrant b
28 RDb Reset Drain, Quadrant b
29 GND Ground
30 VOUTb Video Output, Quadrant b
31 VDDb Output Amplifier Supply, Quadrant b
32 V2B Vertical CCD Clock, Phase 2, Bottom
33 V1B Vertical CCD Clock, Phase 1, Bottom
34 V4B Vertical CCD Clock, Phase 4, Bottom
35 V3B Vertical CCD Clock, Phase 3, Bottom
36 ESD ESD Protection Disable
Pin Name
Description
72 ESD ESD Protection Disable
71 V3T Vertical CCD Clock, Phase 3, Top
70 V4T Vertical CCD Clock, Phase 4, Top
69 V1T Vertical CCD Clock, Phase 1, Top
68 V2T Vertical CCD Clock, Phase 2, Top
67 VDDc Output Amplifier Supply, Quadrant c
66 VOUTc Video Output, Quadrant c
65 GND Ground
64 RDc Reset Drain, Quadrant c
63 Rc Reset Gate, Quadrant c
62 OGc Output Gate, Quadrant c
61 H2SLc Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant c
60 H2Bc Horizontal CCD Clock, Phase 2, Barrier,
Quadrant c
59 H1Bc Horizontal CCD Clock, Phase 1, Barrier,
Quadrant c
58 H1Sc Horizontal CCD Clock, Phase 1,
Storage, Quadrant c
57 H2Sc Horizontal CCD Clock, Phase 2,
Storage, Quadrant c
56 FDGcd Fast Line Dump Gate, Top
55 N/C No Connect
54 FDGcd Fast Line Dump Gate, Top
53 SUB Substrate
52 H1Sd Horizontal CCD Clock, Phase 1,
Storage, Quadrant d
51 H2Sd Horizontal CCD Clock, Phase 2,
Storage, Quadrant d
50 H2Bd Horizontal CCD Clock, Phase 2, Barrier,
Quadrant d
49 H1Bd Horizontal CCD Clock, Phase 1, Barrier,
Quadrant d
48 OGd Output Gate, Quadrant d
47 H2SLd Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant d
46 RDd Reset Drain, Quadrant d
45 Rd Reset Gate, Quadrant d
44 VOUTd Video Output, Quadrant d
43 GND Ground
42 V2T Vertical CCD Clock, Phase 2, Top
41 VDDd Output Amplifier Supply, Quadrant d
40 V4T Vertical CCD Clock, Phase 4, Top
39 V1T Vertical CCD Clock, Phase 1, Top
38 DevID Device Identification
37 V3T Vertical CCD Clock, Phase 3, Top
1. Liked named pins are internally connected and should have a
common drive signal.
2. N/C pins (19, 55) should be left floating.
www.onsemi.com
7

7페이지


구       성 총 30 페이지수
다운로드[ KAI-16050.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
KAI-16050

Interline CCD Image Sensor

ON Semiconductor
ON Semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵